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公开(公告)号：US20060098771A1
公开(公告)日：2006-05-11
申请号：US10983447
申请日：2004-11-08
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , H03K5/133 , H03K5/135 , H03K2005/00286 , H03L7/0812 , H04L7/0337
摘要： A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.
摘要翻译： DPC（300）包括：用于产生时钟信号的频率源（310）; 延迟线（320），用于接收时钟信号并在输出抽头产生相移时钟信号; 数字控制装置（330），用于产生控制信号; 以及用于生成包括顺序逻辑设备（500,510,520）和组合网络的输出信号的加窗选择电路。 一种在DPC中使用的方法包括：基于识别延迟线上的第一输出抽头的期望输出信号接收（400）控制信号; 基于所述控制信号，在所述延迟线上选择（410）至少两个输出抽头用于接收至少两个不同的相移时钟信号; 以及基于所述控制信号和所接收的基本上是所需输出信号的相移时钟信号来产生（420）输出信号。
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2.发明申请Direct digital synthesizer with variable reference for improved spurious performance 有权具有可变参考的直接数字合成器，可提高杂散性能公开(公告)号：US20070222492A1
公开(公告)日：2007-09-27
申请号：US11370689
申请日：2006-03-08
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/131 , H03K2005/00065 , H03L7/1806
摘要： Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.
摘要翻译： 改进在有限分辨率的延迟线中出现的量化误差。 包含数控振荡器（NCO）和数字 - 相位转换器（DPC）的直接数字合成器（DDS）放置在锁相环（PLL）的反馈环路中。 DDS用作压控振荡器（VCO）频率的分数分频器，使得DDS的参考频率变为可变。 然后可以调整由DDS延迟线提供的边缘的对准。 通过利用独立的可调谐延迟元件来减少DDS延迟线中的不匹配误差。
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3.发明申请System and method for introducing dither for reducing spurs in digital-to-time converter direct digital synthesis 有权用于引入抖动以减少数字到时间转换器直接数字合成的系统和方法公开(公告)号：US20060069707A1
公开(公告)日：2006-03-30
申请号：US10954571
申请日：2004-09-30
申请人： Thomas Gradishar , Robert Stengel
发明人： Thomas Gradishar , Robert Stengel
IPC分类号： G06F1/02
CPC分类号： G06F1/025 , G06F2211/902
摘要： A direct digital synthesizer (DDS) (300) that uses a system for reducing spurious emissions in a digital-to-time converter (DTC) (317). The DDS (300) includes one or more dither sources (307) and a random access memory (RAM) (305). The RAM (305) utilizes a look-up table for storing delay error values by using an output of the look-up table which is combined with the dither source (307) to compensate unequal unit delay values in the DTC (317).
摘要翻译： 一种直接数字合成器（DDS）（300），其使用用于减少数字 - 时间转换器（DTC）中的杂散发射的系统（317）。 DDS（300）包括一个或多个抖动源（307）和随机存取存储器（RAM）（305）。 RAM（305）通过使用与抖动源（307）组合的查找表的输出来利用查找表来存储延迟误差值，以补偿DTC（317）中的不相等的单位延迟值。
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