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公开(公告)号：US5450367A
公开(公告)日：1995-09-12
申请号：US880118
申请日：1992-05-07
CPC分类号： G09G5/395 , G11C7/1075
摘要： Stored data for two different images superimposed on one another can be accessed simply and efficiently from the same VRAM. The SAM of the VRAM is divided into multiple-independent portions, each of which respond to its own independently controlled address counter. By loading the image data access into respective SAM portions, and switching data access between SAM portions at the SAM address rate, superimposed data of two different images can be displayed from the same VRAM.
摘要翻译： 可以从相同的VRAM简单有效地访问彼此叠加的两个不同图像的存储数据。 VRAM的SAM被分成多个独立的部分，每个部分响应其自己的独立控制的地址计数器。 通过将图像数据访问加载到各个SAM部分中，并且以SAM地址速率切换SAM部分之间的数据访问，可以从相同的VRAM显示两个不同图像的叠加数据。
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公开(公告)号：US5537650A
公开(公告)日：1996-07-16
申请号：US232536
申请日：1992-12-14
CPC分类号： G06F1/3218 , G09G3/3611 , G09G5/395 , G09G2330/021
摘要： Video subsystem power savings are achieved by shutting off power to unused subcircuits during blanking. Digital circuitry within the video subsystem not used during blanking is shut-down by turning off the clock thereto. Analog circuitry within a digital to analog converter is shut-down by turning off the constant current reference thereto. A functional unit containing digital circuitry within a serializer palette digital to analog converter (SPDAC) is shut-down by turning off the clock thereto during system operation in a mode where the functional unit is not utilized. A computer system having a monochrome display saves power by shutting off DAC digital circuitry clocks and DAC analog circuitry constant current references of all DACs but one. A portable computer with a liquid crystal display (LCD), a SPDAC for driving an external display and a LCD controller, saves power by shutting down video subsystem functional units and analog DAC circuitry not used for driving the LCD. Digital circuitry within the LCD controller is shut-down when an external display is being driven. In a portable computer operating in a SUSPEND state, video subsystem functional units are shut-down.
摘要翻译： 通过在消隐期间关闭未使用的子电路的电源来实现视频子系统的功率节省。 在消隐期间未使用的视频子系统内的数字电路通过关闭时钟来关闭。 通过关闭数模转换器的恒定电流基准来关闭数模转换器中的模拟电路。 在串行器调色板数模转换器（SPDAC）中包含数字电路的功能单元在不使用功能单元的模式下在系统操作期间关闭时钟来关闭。 具有单色显示器的计算机系统通过关闭所有DAC的DAC数字电路时钟和DAC模拟电路恒定电流基准来节省功率，但一个。 具有液晶显示器（LCD）的便携式计算机，用于驱动外部显示器的SPDAC和LCD控制器，通过关闭不用于驱动LCD的视频子系统功能单元和模拟DAC电路来节省电力。 当外部显示器被驱动时，LCD控制器内的数字电路被关闭。 在SUSPEND状态下运行的便携式计算机中，视频子系统功能单元被关闭。
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3.发明授权Graphics display subsystem that allows per pixel double buffer display rejection 失效图形显示子系统允许每像素双缓冲显示拒绝
公开(公告)号：US5629723A
公开(公告)日：1997-05-13
申请号：US528866
申请日：1995-09-15
摘要： A graphics display subsystem that allows rejection of double buffer display of pixel data in a graphics layer is provided. The subsystem has a memory containing a plurality of pixels represented by binary bits, wherein each pixel is divided into two or more sub-pixel fields, and wherein one or more bits of a particular sub-pixel field of a given pixel are set to a predetermined double buffer reject value when the given pixel corresponds to a single buffer display application. A double buffer reject circuit compares one or more bits of a double buffer sub-pixel field of a given pixel with a predetermined double buffer reject value to determine equality of the one or more bits and the predetermined value, wherein the given pixel is represented by binary bits and wherein the given pixel is divided into two or more sub-pixel fields including the double buffer sub-pixel field. The double buffer reject circuit receives a buffer select signal selecting one of the two or more sub-pixel fields of the given pixel to be accessed during a current display frame. In response, the double buffer reject circuit accesses the selected sub-pixel field of the given pixel when the buffer select signal does not select the double buffer sub-pixel field or when the buffer select signal selects the double buffer sub-pixel field and the comparison does not show equality, and further the double buffer reject circuit accesses one of the two or more sub-pixel fields of the given pixel that is not the double buffer sub-pixel field when the buffer select signal selects the double buffer sub-pixel field and the comparison shows equality. A digital-to-analog converter in communication with the double buffer reject circuit receives the pixel data contained in the sub-pixel field accessed by the double buffer reject circuit and converts the pixel data into analog video signals for driving a monitor display device.
摘要翻译： 提供允许拒绝图形层中的像素数据的双缓冲器显示的图形显示子系统。 子系统具有包含由二进制位表示的多个像素的存储器，其中每个像素被分成两个或更多个子像素场，并且其中给定像素的特定子像素场的一个或多个位被设置为 当给定像素对应于单个缓冲器显示应用时，预定的双缓冲器拒绝值。 双缓冲器拒绝电路将给定像素的双缓冲器子像素场的一个或多个比特与预定的双缓冲区拒绝值进行比较，以确定一个或多个比特和预定值的相等性，其中给定像素由 二进制位，并且其中给定像素被分成包括双缓冲器子像素场的两个或多个子像素场。 双缓冲器抑制电路接收在当前显示帧期间选择要访问的给定像素的两个或多个子像素场中的一个的缓冲器选择信号。 作为响应，当缓冲器选择信号不选择双缓冲器子像素场时，或者当缓冲器选择信号选择双缓冲器子像素场时，双缓冲区拒绝电路访问给定像素的选择子像素场，并且 比较不显示相等性，并且当缓冲器选择信号选择双缓冲器子像素时，双缓冲区拒绝电路进一步访问给定像素中不是双缓冲器子像素场的两个或更多个子像素场中的一个 字段和比较显示相等。 与双缓冲器抑制电路通信的数模转换器接收由双缓冲器抑制电路访问的子像素场中包含的像素数据，并将像素数据转换为用于驱动监视器显示设备的模拟视频信号。
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公开(公告)号：US5528602A
公开(公告)日：1996-06-18
申请号：US400699
申请日：1995-03-09
CPC分类号： G11C29/003
摘要： The presence or absence of a property in a computer subsystem is determined using a multiple input shift register (MISR). A subsystem device operates on predetermined test data to produce output data. The MISR operates on the output data to produce a final test value dependent on the output data. The property has a known final MISR value associated with the device under test and the test data. The MISR final test value is read and compared to the known final value for the property. If the two values are the same, the property exists in the system. In a second embodiment, a property from among a set of known possible properties or variations of a property is determined. In a specific application of the second embodiment, the length of a serial access memory (SAM) portion of a video random access memory (VRAM) is determined.
摘要翻译： 使用多输入移位寄存器（MISR）确定计算机子系统中的属性的存在或不存在。 子系统设备对预定的测试数据进行操作以产生输出数据。 MISR对输出数据进行操作，以产生取决于输出数据的最终测试值。 该属性具有与被测设备相关联的已知最终MISR值和测试数据。 读取MISR最终测试值并与该属性的已知最终值进行比较。 如果两个值相同，则该属性存在于系统中。 在第二实施例中，确定一组已知的可能性质或性质的变化之间的性质。 在第二实施例的具体应用中，确定视频随机存取存储器（VRAM）的串行存取存储器（SAM）部分的长度。
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公开(公告)号：US5179372A
公开(公告)日：1993-01-12
申请号：US676659
申请日：1991-03-28
申请人： Roderick M. P. West , Todd Williams
发明人： Roderick M. P. West , Todd Williams
CPC分类号： G09G5/395 , G09G2360/126
摘要： A Video Random Access Memory device wherein full and efficient use of a serial access memory portion provides a simple and efficient means of avoiding Mid-Line Reloads. Selected parts of two different rows in a random access memory portion are transferred simultaneously to the serial access memory portion via addressable transfer gates under the control of address/control logic.
摘要翻译： 一种视频随机存取存储器件，其中全面有效地使用串行存取存储器部分提供了避免中线重载的简单有效的手段。 在地址/控制逻辑的控制下，随机访问存储器部分中的两行不同行的选定部分被同时传送到可访问传输门的串行访问存储器部分。
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公开(公告)号：US4672579A
公开(公告)日：1987-06-09
申请号：US737604
申请日：1985-05-24
IPC分类号： G09G5/22 , G06F3/153 , G09G5/02 , G11C11/411 , G11C11/416 , H01L27/02 , G11C7/00
CPC分类号： G11C11/416 , G11C11/4113 , H01L27/0233
摘要： Semiconductor integrated word organized store comprising a two-dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled merged transistor logic (MTL) gates having a structure providing a vertical inverting base transistor and two complementary lateral injector transistors. A cell is driven by read/write logic pulses applied to the word lines and bit lines only. To read the contents of a word from the array, read logic drives the read injectors of the cells constituting the word at a high injector current level and the read injectors of all other cells at a low injector current level. To select a word for writing, the read logic drives the read injectors of the cells comprising the word at a low injector current level and all other cells at a high injector current level. The contents of the selected word may then be changed by differentially driving the cell write injectors over the bit lines. Output multiplexing of cells storing corresponding bit positions in the words is achieved simply by connecting the cell outputs together (dot ANDing). Logical output discrimination and interfacing is achieved by comparing the multiplexed output current with a threshold current. If the output current is less than the threshold current, the cell is storing a logical ONE. If the output current is greater than the threshold current, the cell is storing a logical ZERO.
摘要翻译： 半导体集成词组织存储包括由正交字线和位线对链接的双稳态存储单元的二维阵列。 每个单元由具有提供垂直反相基极晶体管和两个互补侧向注入器晶体管的结构的两个交叉耦合的合并晶体管逻辑（MTL）门组成。 单元由仅写入字线和位线的读/写逻辑脉冲驱动。 为了从阵列中读取单词的内容，读取逻辑以高喷射器电流水平驱动构成单词的单元的读取注入器，并以低喷射器电流水平驱动所有其他单元的读取注入器。 为了选择用于写入的字，读逻辑驱动包含低注射器电流电平的单词的单元的读取注入器以及高注射器电流水平的所有其它单元。 然后可以通过在位线上差分驱动单元写入注入器来改变所选择的单词的内容。 简单地通过将单元输出连接在一起（点ANDing）来实现在单词中存储相应位位置的单元的输出多路复用。 通过将多路复用的输出电流与阈值电流进行比较来实现逻辑输出鉴别和接口。 如果输出电流小于阈值电流，则单元正在存储逻辑1。 如果输出电流大于阈值电流，则单元正在存储逻辑“零”。
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公开(公告)号：US5631672A
公开(公告)日：1997-05-20
申请号：US499557
申请日：1995-07-07
IPC分类号： G09G5/00 , G09G5/395 , G11C7/10 , G11C11/401
CPC分类号： G09G5/395 , G11C7/1075
摘要： A Video-RAM semiconductor memory device comprised of a RAM army having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulus such as a RAS clock from an external controller indicating a coarse timing location for a data transfer between the RAM array and the serial access array. The control logic then provides control signals, that are internally synchronized with a serial clock, and that occur during a period that a tap pointer is equal to a value one less than a programmable target value or an input target address. This causes a row in the RAM array corresponding to an input row address to be transferred between the RAM array and the serial access array.
摘要翻译： 一种由具有用于输入行，列和目标地址的地址输入的RAM陆军和具有串行输出端口的串行访问阵列组成的视频RAM半导体存储器件。 视频RAM具有地址/控制逻辑，其检测来自外部控制器的诸如RAS时钟的激励，指示用于RAM阵列和串行访问阵列之间的数据传输的粗略定时位置。 然后，控制逻辑提供与串行时钟在内部同步的控制信号，并且在分针指针等于小于可编程目标值或输入目标地址的值的周期期间发生。 这使得RAM阵列中对应于输入行地址的一行在RAM阵列和串行存取阵列之间传输。
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公开(公告)号：US5604518A
公开(公告)日：1997-02-18
申请号：US220090
申请日：1994-03-30
IPC分类号： G06F12/00 , G09G5/06 , G11C5/06 , G11C11/401 , G11C11/408
CPC分类号： G11C5/066
摘要： An integrated memory structure, and associated processing method, is coupled to receive address data and control data. The memory structure includes a composite memory array having a first array portion and a second array portion which are separately addressable. The first array portion is accessed using at least some of the address data as a first address signal and the second array portion is addressed using at least some of the control data also as a second address signal. The memory structure is presented herein by way of example for a serial palette digital-to-analog (SPD) device, and incorporates indirect color mode, direct color mode, overlay color mode and cursor color mode processing in a single macro. When in direct color mode, access to the memory array is disabled and address data is transferred directly to an output of the memory structure as data out.
摘要翻译： 一个集成的存储器结构和相关联的处理方法被耦合以接收地址数据和控制数据。 存储器结构包括具有可单独寻址的第一阵列部分和第二阵列部分的复合存储器阵列。 使用至少一些地址数据作为第一地址信号来访问第一阵列部分，并且使用至少一些控制数据也将第二阵列部分寻址为第二地址信号。 存储器结构在这里作为示例用于串行调色板数模（SPD）设备，并且在单个宏中并入间接颜色模式，直接颜色模式，叠加颜色模式和光标颜色模式处理。 当处于直接颜色模式时，对存储器阵列的访问被禁用，并且将地址数据直接传送到作为数据输出的存储器结构的输出。
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公开(公告)号：US5121360A
公开(公告)日：1992-06-09
申请号：US773736
申请日：1991-10-09
申请人： Roderick M. P. West , Todd Williams
发明人： Roderick M. P. West , Todd Williams
CPC分类号： G09G5/39 , G09G2310/0224 , G09G5/399
摘要： A Video Random Access Memory device wherein full and efficient use of a serial access memory portion provides a simple and efficient means of avoiding Mid-Line Reloads. Selected parts of two different rows in a random access memory portion are transferred simultaneously to the serial access memory portion via addressable transfer gates under the control of address/control logic.
摘要翻译： 一种视频随机存取存储器件，其中全面有效地使用串行存取存储器部分提供了避免中线重载的简单有效的手段。 在地址/控制逻辑的控制下，随机访问存储器部分中的两行不同行的选定部分被同时传送到可访问传输门的串行访问存储器部分。
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