公开(公告)号：US08085518B2

公开(公告)日：2011-12-27

申请号：US11436235

申请日：2006-05-18

申请人： Nirmal Chaudhary ,  Christian Russ ,  Thomas Schulz

发明人： Nirmal Chaudhary ,  Christian Russ ,  Thomas Schulz

IPC分类号： H02H9/00

CPC分类号： H01L27/1211 ,  H01L27/0266 ,  H01L29/785 ,  H03K17/08142 ,  H03K17/122 ,  H03K17/302 ,  H03K17/6871

摘要： An electronic circuit and method for producing the electronic circuit, where the electronic circuit includes a functional circuit including at least one multigate functional field effect transistor and an ESD protection circuit including at least one multigate ESD protection field effect transistor. The multigate protection field effect transistor is a transistor that is partially depleted of electrical charge carriers, and the trigger voltage of the multigate protection field effect transistor is less than the trigger voltage of the multigate functional field effect transistor.

摘要翻译： 一种用于制造电子电路的电子电路和方法，其中电子电路包括包括至少一个多功能场效应晶体管的功能电路和包括至少一个多重ESD保护场效应晶体管的ESD保护电路。 多栅极保护场效应晶体管是部分耗尽电荷载流子的晶体管，并且多栅极保护场效应晶体管的触发电压小于多功能场效应晶体管的触发电压。

公开(公告)号：US07094650B2

公开(公告)日：2006-08-22

申请号：US11039173

申请日：2005-01-20

申请人： Nirmal Chaudhary ,  Thomas Schulz ,  Weize Xiong ,  Craig Huffman

发明人： Nirmal Chaudhary ,  Thomas Schulz ,  Weize Xiong ,  Craig Huffman

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/66795 ,  H01L29/785

摘要： In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.

摘要翻译： 在形成半导体器件的方法中，在包括具有锐利掉落的形貌的衬底上形成自平面化导电层。 自平坦化导电层的特征在于比底层形貌基本上更平坦的表面。 作为自平坦化层的结果，可以在导电层上形成具有更均匀厚度的掩模层。 由于掩模层具有更均匀的厚度，所以掩蔽层可以容易地被图案化，而不会对下面的材料造成损害。 除了别的以外，这些技术可以用于制造没有在鳍片和源极/漏极区域周围形成的寄生间隔物的FinFET。

公开(公告)号：US20060160312A1

公开(公告)日：2006-07-20

申请号：US11039173

申请日：2005-01-20

申请人： Nirmal Chaudhary ,  Thomas Schulz ,  Weize Xiong ,  Craig Huffman

发明人： Nirmal Chaudhary ,  Thomas Schulz ,  Weize Xiong ,  Craig Huffman

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/66795 ,  H01L29/785

摘要： In a method of forming a semiconductor device, a self-planarizing conductive layer is formed over a substrate that includes a topography having sharp drop-offs. The self-planarizing conductive layer is characterized by a substantially flatter surface than the underlying topography. As a result of the self-planarizing layer, a masking layer having a more uniform thickness may be formed over the conductive layer. Because the masking layer has a more uniform thickness, the masking layer may easily be patterned without causing damage to the underlying materials. These techniques may be used to fabricate, among other things, a FinFET without parasitic spacers formed around the fins and the source/drain regions.

摘要翻译： 在形成半导体器件的方法中，在包括具有锐利掉落的形貌的衬底上形成自平面化导电层。 自平坦化导电层的特征在于比底层形貌基本上更平坦的表面。 作为自平坦化层的结果，可以在导电层上形成具有更均匀厚度的掩模层。 由于掩模层具有更均匀的厚度，所以掩蔽层可以容易地被图案化，而不会对下面的材料造成损害。 除了别的以外，这些技术可以用于制造没有在鳍片和源极/漏极区域周围形成的寄生间隔物的FinFET。

公开(公告)号：US07638370B2

公开(公告)日：2009-12-29

申请号：US11800984

申请日：2007-05-08

申请人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

发明人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

IPC分类号： H01L29/78 ,  H01L21/332

CPC分类号： H01L29/78624 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

摘要翻译： 在电子部件的制造方法中，在基板上或上方形成第一掺杂连接区域和第二掺杂连接区域， 在所述第一掺杂连接区域和所述第二掺杂连接区域之间形成体区; 在身体区域上或上方形成彼此分离的至少两个栅极区域; 通过引入掺杂剂原子来掺杂体区的至少一个部分区域，其中通过形成在至少两个分开的栅极区域之间的至少一个中间区域将掺杂剂原子引入到体区的至少一个部分区域中 。

公开(公告)号：US20100062573A1

公开(公告)日：2010-03-11

申请号：US12620930

申请日：2009-11-18

申请人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

发明人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

IPC分类号： H01L21/332

CPC分类号： H01L29/78624 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

摘要翻译： 在电子部件的制造方法中，在基板上或上方形成第一掺杂连接区域和第二掺杂连接区域， 在所述第一掺杂连接区域和所述第二掺杂连接区域之间形成体区; 在身体区域上或上方形成彼此分离的至少两个栅极区域; 通过引入掺杂剂原子来掺杂体区的至少一个部分区域，其中通过形成在至少两个分开的栅极区域之间的至少一个中间区域将掺杂剂原子引入到体区的至少一个部分区域中 。

公开(公告)号：US20080116515A1

公开(公告)日：2008-05-22

申请号：US11561170

申请日：2006-11-17

申请人： Harald Gossner ,  Christian Russ ,  Jens Schneider ,  Thomas Schulz

发明人： Harald Gossner ,  Christian Russ ,  Jens Schneider ,  Thomas Schulz

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L23/367 ,  H01L27/0248 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed

摘要翻译： 本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。 所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态 靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。 还公开了其他实施例

公开(公告)号：US20080067587A1

公开(公告)日：2008-03-20

申请号：US11800984

申请日：2007-05-08

申请人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

发明人： Harald Gossner ,  Thomas Schulz ,  Christian Russ ,  Gerhard Knoblinger

IPC分类号： H01L29/78 ,  H01L21/332 ,  H01L21/336

CPC分类号： H01L29/78624 ,  H01L21/26586 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203 ,  H01L29/66393 ,  H01L29/7436 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions.

摘要翻译： 在电子部件的制造方法中，在基板上或上方形成第一掺杂连接区域和第二掺杂连接区域， 在所述第一掺杂连接区域和所述第二掺杂连接区域之间形成体区; 在身体区域上或上方形成彼此分离的至少两个栅极区域; 通过引入掺杂剂原子来掺杂体区的至少一个部分区域，其中通过形成在至少两个分开的栅极区域之间的至少一个中间区域将掺杂剂原子引入到体区的至少一个部分区域中 。

公开(公告)号：US20070025034A1

公开(公告)日：2007-02-01

申请号：US11436235

申请日：2006-05-18

申请人： Nimal Chaudhary ,  Christian Russ ,  Thomas Schulz

发明人： Nimal Chaudhary ,  Christian Russ ,  Thomas Schulz

IPC分类号： H02H9/00

CPC分类号： H01L27/1211 ,  H01L27/0266 ,  H01L29/785 ,  H03K17/08142 ,  H03K17/122 ,  H03K17/302 ,  H03K17/6871

摘要： An electronic circuit and method for producing the electronic circuit, where the electronic circuit includes a functional circuit including at least one multigate functional field effect transistor and an ESD protection circuit including at least one multigate ESD protection field effect transistor. The multigate protection field effect transistor is a transistor that is partially depleted of electrical charge carriers, and the trigger voltage of the multigate protection field effect transistor is less than the trigger voltage of the multigate functional field effect transistor.

摘要翻译： 一种用于制造电子电路的电子电路和方法，其中电子电路包括包括至少一个多功能场效应晶体管的功能电路和包括至少一个多重ESD保护场效应晶体管的ESD保护电路。 多栅极保护场效应晶体管是部分耗尽电荷载流子的晶体管，并且多栅极保护场效应晶体管的触发电压小于多功能场效应晶体管的触发电压。

公开(公告)号：US08072061B2

公开(公告)日：2011-12-06

申请号：US12720700

申请日：2010-03-10

申请人： Harald Gossner ,  Christian Russ ,  Thomas Schulz ,  Jens Schneider

发明人： Harald Gossner ,  Christian Russ ,  Thomas Schulz ,  Jens Schneider

IPC分类号： H01L23/34

CPC分类号： H01L29/785 ,  H01L23/367 ,  H01L27/0248 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region.

摘要翻译： 本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。 所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态 靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。

公开(公告)号：US07678632B2

公开(公告)日：2010-03-16

申请号：US11561170

申请日：2006-11-17

申请人： Harald Gossner ,  Christian Russ ,  Jens Schneider ,  Thomas Schulz

发明人： Harald Gossner ,  Christian Russ ,  Jens Schneider ,  Thomas Schulz

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L23/367 ,  H01L27/0248 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed.

摘要翻译： 本文讨论的一些实施例包括具有源极区域，漏极区域和翅片阵列的半导体，其可操作地耦合到栅极区域，以控制流过源极区域和漏极区域之间的鳍片的电流。 所述半导体还具有至少一部分形成有至少部分热容量等于或大于所述源极区域，漏极区域和散热片阵列的热容量的冷却元件的冷却元件，所述冷却元件处于闭合状态 靠近与阵列的鳍片，源极区域和漏极区域电隔离的翅片阵列的翅片。 还公开了其他实施例。