公开(公告)号：US20080258764A1

公开(公告)日：2008-10-23

申请号：US12138281

申请日：2008-06-12

Applicant: Nitin Deshmukh ,  Kailash Digari

Inventor： Nitin Deshmukh ,  Kailash Digari

IPC: H03K19/177

CPC classification number: H03K19/17736

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains.

Abstract translation: 互连结构可实现可编程逻辑中的间接路由。 该结构包括包括多个路由线的域和连接到域中的第一路由线的输入线。 开关盒连接到第一路由线路，并被配置为将输入线路间接连接到域中的其他路由线路。 在一些实施例中，域包括被配置为将一个域的路由线连接到其他域的任何路由线路的可编程开关。

公开(公告)号：US07307452B2

公开(公告)日：2007-12-11

申请号：US11258616

申请日：2005-10-25

Applicant: Nitin Deshmukh ,  Kailash Digari

Inventor： Nitin Deshmukh ,  Kailash Digari

IPC: H01L25/00 ,  H03K19/177

CPC classification number: H03K19/17736

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract translation: 互连结构可实现可编程逻辑中的间接路由。 该结构包括多个路由线路，以及耦合到多个路由线路的交换机盒和连接盒。 连接箱包括每个路由轨道中的至少一个可编程开关。 连接到相同互连矩阵的每个连接盒中的可编程开关的位置与其他连接盒的相应路线轨迹中的所述可编程开关的位置不同，从而利用所述开关盒的连接用于输入连接并增加 连接的灵活性。

公开(公告)号：US07755388B2

公开(公告)日：2010-07-13

申请号：US12138281

申请日：2008-06-12

Applicant: Nitin Deshmukh ,  Kailash Digari

Inventor： Nitin Deshmukh ,  Kailash Digari

IPC: H01L25/00 ,  H03K19/177

CPC classification number: H03K19/17736

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a domain comprising a plurality of routing lines and an input line connected to a first routing line in the domain. A switch box is connected to the first routing line and is configured to indirectly connect the input line to the other routing lines in the domain. In some embodiments a domain includes programmable switches that are configured to connect a routing line of one domain to any routing line of the other domains.

Abstract translation: 互连结构可实现可编程逻辑中的间接路由。 该结构包括包括多个路由线的域和连接到域中的第一路由线的输入线。 开关盒连接到第一路由线，并被配置为将输入线间接连接到域中的其他路由线。 在一些实施例中，域包括被配置为将一个域的路由线连接到其他域的任何路由线路的可编程开关。

公开(公告)号：US20080084230A1

公开(公告)日：2008-04-10

申请号：US11952524

申请日：2007-12-07

Applicant: Nitin Deshmukh ,  Kailash Digari

Inventor： Nitin Deshmukh ,  Kailash Digari

IPC: H01L25/00

CPC classification number: H03K19/17736

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract translation: 互连结构可实现可编程逻辑中的间接路由。 该结构包括多个路由线路，以及耦合到多个路由线路的交换机盒和连接盒。 连接箱包括每个路由轨道中的至少一个可编程开关。 连接到相同互连矩阵的每个连接盒中的可编程开关的位置与其他连接盒的相应路线轨迹中的所述可编程开关的位置不同，从而利用所述开关盒的连接用于输入连接并增加 连接的灵活性。

公开(公告)号：US07414433B2

公开(公告)日：2008-08-19

申请号：US11952524

申请日：2007-12-07

Applicant: Nitin Deshmukh ,  Kailash Digari

Inventor： Nitin Deshmukh ,  Kailash Digari

IPC: H01L25/00 ,  H03K19/177

CPC classification number: H03K19/17736

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract translation: 互连结构可实现可编程逻辑中的间接路由。 该结构包括多个路由线路，以及耦合到多个路由线路的交换机盒和连接盒。 连接箱包括每个路由轨道中的至少一个可编程开关。 连接到相同互连矩阵的每个连接盒中的可编程开关的位置与其他连接盒的相应路线轨迹中的所述可编程开关的位置不同，从而利用所述开关盒的连接用于输入连接并增加 连接的灵活性。

公开(公告)号：US20060139055A1

公开(公告)日：2006-06-29

申请号：US11258616

申请日：2005-10-25

Applicant: Nitin Deshmukh ,  Kailash Digari

Inventor： Nitin Deshmukh ,  Kailash Digari

IPC: H03K19/177

CPC classification number: H03K19/17736

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract translation: 互连结构可实现可编程逻辑中的间接路由。 该结构包括多个路由线路，以及耦合到多个路由线路的交换机盒和连接盒。 连接箱包括每个路由轨道中的至少一个可编程开关。 连接到相同互连矩阵的每个连接盒中的可编程开关的位置与其他连接盒的相应路线轨迹中的所述可编程开关的位置不同，从而利用所述开关盒的连接用于输入连接并增加 连接的灵活性。

公开(公告)号：US06864714B2

公开(公告)日：2005-03-08

申请号：US10460040

申请日：2003-06-10

Applicant: Kailash Digari ,  Nitin Deshmukh

Inventor： Kailash Digari ,  Nitin Deshmukh

IPC: H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17772 ,  H03K19/1737 ,  H03K19/17728

Abstract: The present invention provides a Programmable Logic Device (PLD) incorporating a two-input multiplexer for providing a Cascade Logic output and having a Cascade Logic input coupled to a select line. A two-input multiplexer provides the desired configurable Cascade Logic function, and an initialization circuit sets the initial value for the Cascade logic under control of an initialization configuration bit. The multiplexer that provides the Cascade Logic output also provides the desired configurable Cascade Logic function using the Look-up table (LUT) and configuration bits.

Abstract translation: 本发明提供了一种结合了双输入多路复用器的可编程逻辑器件（PLD），用于提供级联逻辑输出并具有耦合到选择线的级联逻辑输入。 双输入多路复用器提供所需的可配置级联逻辑功能，初始化电路在初始化配置位的控制下设置级联逻辑的初始值。 提供级联逻辑输出的多路复用器还使用查找表（LUT）和配置位提供所需的可配置级联逻辑功能。

公开(公告)号：US20060119388A1

公开(公告)日：2006-06-08

申请号：US11264674

申请日：2005-11-01

Applicant: Deboleena Minz ,  Kailash Digari

Inventor： Deboleena Minz ,  Kailash Digari

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17732

Abstract: An improved FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.

Abstract translation: 一种改进的FPGA，包括用于提供选择性数据路由的直接互连结构，而不强调通用路由资源并且实现FPGA内的高速率的数据交换。 至少两个IP核通过所述直接互连结构相互连接，以便能够在所述IP核的端口之间同时进行数据交互，并且用于在所述IP核之间提供可配置的总线宽度路由，以及连接到所述IP核的多个逻辑块 通过所述直接互连结构来实现在所述IP核和所述多个逻辑块之间的同时数据路由。

公开(公告)号：US08112466B2

公开(公告)日：2012-02-07

申请号：US11238123

申请日：2005-09-28

Applicant: Deboleena Minz ,  Kailash Digari

Inventor： Deboleena Minz ,  Kailash Digari

IPC: G06F7/38

CPC classification number: G06F7/57 ,  G06F15/7867

Abstract: An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.

Abstract translation: 使用一个或多个计算块，每个块具有乘法器，累加器和多路复用器的现场可编程门阵列（FPGA）中的DSP功能的有效实现。 该结构以快速和高度紧凑的方式实现了大多数常见DSP方程。 提供了一种利用专用DSP线路级联这些块的新颖方法，这导致了n阶段MAC操作的非常简单和精通的实现。

公开(公告)号：US07961004B2

公开(公告)日：2011-06-14

申请号：US12645236

申请日：2009-12-22

Applicant: Deboleena Minz ,  Kailash Digari

Inventor： Deboleena Minz ,  Kailash Digari

IPC: H01L25/00

CPC classification number: H03K19/17736 ,  H03K19/17732

Abstract: A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks.

Abstract translation: 一种FPGA，包括用于提供选择性数据路由的直接互连结构，而不强调通用路由资源并且实现FPGA内的高速数据交换。 至少两个IP核通过所述直接互连结构相互连接，以便能够在所述IP核的端口之间同时进行数据交互，并且用于在所述IP核之间提供可配置的总线宽度路由，以及连接到所述IP核的多个逻辑块 通过所述直接互连结构来实现在所述IP核和所述多个逻辑块之间的同时数据路由。