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公开(公告)号：US20220247423A1
公开(公告)日：2022-08-04
申请号：US17616643
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： DAIGUO XU , HEQUAN JIANG , RUZHANG LI , JIANAN WANG , GUANGBING CHEN , YUXIN WANG , DONGBING FU , LIANG LI , YAN WANG
摘要： SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel.
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公开(公告)号：US20190027563A1
公开(公告)日：2019-01-24
申请号：US16068098
申请日：2016-04-01
发明人： KAIZHOU TAN , GANGYI HU , ZHAOHUAN TANG , JIANAN WANG , YONGHUI YANG , YI ZHONG , YANG CAO , YONG LIU , KUNFENG ZHU
IPC分类号： H01L29/40 , H01L29/10 , H01L29/06 , H01L29/78 , H01L29/861 , H01L29/872 , H01L29/36 , H01L21/02
摘要： A semiconductor cell structure and power semiconductor device, wherein, the semiconductor cell structure includes: a highly-doped semiconductor material region, an epitaxial layer, a dielectric insulating layer, a semi-insulating material, and an active device region, a deep groove is further etched on the epitaxial layer, the deep groove vertically extends into the highly-doped semiconductor material region, the dielectric insulating layer is formed on a side wall inside the deep groove, and the deep groove is filled with the semi-insulating material. The cell structure can be applied to the power semiconductor device during actual application, the present invention dramatically reduces the difficulty of the process implementation, relaxes the harsh requirements on charge balance, broadens the tolerant charge mismatch percentage by approximately ten times, and also improves the long-term reliability of normal operation of the device cell at the same time.
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公开(公告)号：US20220091184A1
公开(公告)日：2022-03-24
申请号：US17602993
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： MINGYUAN XU , LIANG LI , JUN LIU , XIAOFENG SHEN , JIANAN WANG , DONGBING FU , GUANGBING CHEN , XINGFA HUANG , XI CHEN
IPC分类号： G01R31/317 , H03K19/0948
摘要： The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK−) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK−) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.
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公开(公告)号：US20220247354A1
公开(公告)日：2022-08-04
申请号：US17616642
申请日：2020-01-07
申请人： NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION , CHONGQING GIGACHIP TECHNOLOGY CO. LTD.
发明人： RONGBIN HU , ZIQIANG YI , GANG ZHOU , DONG TANG , NING TANG , DAIGUO XU , JIANAN WANG , GUANGBING CHEN , DONGBING FU
摘要： The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents., and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the sensor system.
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公开(公告)号：US20190115903A1
公开(公告)日：2019-04-18
申请号：US16064658
申请日：2017-01-19
发明人： DAIGUO XU , GANGYI HU , RUZHANG LI , JIANAN WANG , GUANGBING CHEN , YUXIN WANG , DONGBING FU , TAO LIU , LU LIU , MINMING DENG , HANFU SHI , XU WANG
CPC分类号： H03K3/012 , H03K3/037 , H03K3/356139 , H03K3/356173 , H03K3/356182 , H03K3/35625 , H03K19/0013 , H03K19/0016
摘要： A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.
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