公开(公告)号：US4892613A

公开(公告)日：1990-01-09

申请号：US290076

申请日：1988-12-27

申请人： Noboru Motai ,  Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yaeko Suzuki ,  Yoshihisa Ogiwara ,  Kazunori Saito ,  Keiko Shibuki

发明人： Noboru Motai ,  Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yaeko Suzuki ,  Yoshihisa Ogiwara ,  Kazunori Saito ,  Keiko Shibuki

IPC分类号： H01L21/302 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L21/0274 ,  H01L21/28008 ,  H01L29/78633

摘要： A light shielding thin film is provided on a light transmitting substrate, and the film is covered by a photoresist. The photoresist is exposed and developed to form a pattern, and the film is etched using the pattern as a mask. The pattern is then exposed through the substrate, using the film as a mask, the pattern then being developed to form a pattern of reduced size. The film is then etched using the reduced size pattern as a mask.

摘要翻译： 在透光性基板上设置遮光薄膜，由光致抗蚀剂覆盖薄膜。 光致抗蚀剂被曝光和显影以形成图案，并且使用该图案作为掩模蚀刻该膜。 然后将该图案通过基底曝光，使用该膜作为掩模，然后将该图案显影以形成尺寸减小的图案。 然后使用减小尺寸的图案作为掩模蚀刻该膜。

公开(公告)号：US5109260A

公开(公告)日：1992-04-28

申请号：US564815

申请日：1990-08-08

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624

摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

摘要翻译： 硅薄膜晶体管阵列包括阵列状形式的多个硅薄膜晶体管，每个硅薄膜晶体管包括绝缘基板，形成在绝缘基板上的栅电极，形成在绝缘基板上的栅绝缘层， 栅电极，一对第一杂质含有在栅极绝缘层上形成的跨越栅电极的端部的硅层，形成在一对第一杂质上的本征硅层含有硅层和在 一对第一杂质之间的栅极绝缘层包含硅层，以便连接一对第一杂质含硅层，形成在本征硅层上的保护绝缘层，以及形成在源极电极和漏电极 该对第一杂质的接触部分含有硅层; 用于将硅薄膜晶体管的栅电极彼此连接的栅极布线; 以及用于将硅薄膜晶体管的源电极彼此连接的源极布线。

公开(公告)号：US5071779A

公开(公告)日：1991-12-10

申请号：US494037

申请日：1990-03-15

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/7866 ,  H01L29/78669

摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

公开(公告)号：US5021850A

公开(公告)日：1991-06-04

申请号：US377873

申请日：1989-07-10

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/7866 ,  H01L29/78669

摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

摘要翻译： 硅薄膜晶体管阵列包括阵列状形式的多个硅薄膜晶体管，每个硅薄膜晶体管包括绝缘基板，形成在绝缘基板上的栅电极，形成在绝缘基板上的栅绝缘层， 栅电极，一对第一杂质含有在栅极绝缘层上形成的跨越栅电极的端部的硅层，形成在一对第一杂质上的本征硅层含有硅层和在 一对第一杂质之间的栅极绝缘层包含硅层，以便连接一对第一杂质含硅层，形成在本征硅层上的保护绝缘层，以及形成在源极电极和漏电极 该对第一杂质的接触部分含有硅层; 用于将硅薄膜晶体管的栅电极彼此连接的栅极布线; 以及用于将硅薄膜晶体管的源电极彼此连接的源极布线。

公开(公告)号：US4979006A

公开(公告)日：1990-12-18

申请号：US358035

申请日：1989-05-26

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L27/12 ,  G02F1/136 ,  G02F1/1368 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78669

摘要： A reverse staggered type silicon thin film transistor includes a substrate having a gate electrode; a gate insulating layer on the substrate and the gate electrode, the gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, the lower layer silicon film being formed at a first temperature and with a first thickness; an upper layer silicon film formed on the transistor-forming portion of the gate insulating layer at a second temperature which is lower than the first temperature and with a second thickness greater than the first thickness; and n-type silicon layer on the upper layer silicon film and in contact therewith; a source electrode on the n-type silicon layer; and a drain electrode on the n-type silicon layer.

摘要翻译： 反向交错型硅薄膜晶体管包括具有栅电极的基板; 在所述基板上的栅极绝缘层和所述栅电极，所述栅极绝缘层具有晶体管形成部分; 在所述栅极绝缘层的所述晶体管形成部分上与其接触的下层硅膜，所述下层硅膜以第一温度和第一厚度形成; 上层硅膜，形成在所述栅极绝缘层的所述晶体管形成部分上，所述第二温度低于所述第一温度，第二厚度大于所述第一厚度; 和n型硅层在上层硅膜上并与其接触; n型硅层上的源电极; 和n型硅层上的漏电极。

公开(公告)号：US5114869A

公开(公告)日：1992-05-19

申请号：US358039

申请日：1989-05-26

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L27/12 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  Y10S438/919

摘要： A method for producing a reverse staggered type silicon thin film transistor includes the steps of forming a gate insulating layer on a substrate having a gate electrode, the gate insulating layer having a transistor-forming portion; forming an intrinsic silicon film on the transistor-forming portion of the gate insulating layer; forming an n-type silicon layer on the intrinsic silicon layer; forming a source electrode on the n-type silicon layer; forming a drain electrode on the n-type silicon layer; forming a resist layer on the source electrode and drain electrode and having the same shape thereof; subsequently removing a portion of the n-type silicon layer by using the resist layer as a mask, such that there remains a predetermined thickness of the n-type silicon layer; and doping the predetermined thickness of the n-type silicon layer with p-type impurities by using the resist layer as a mask.

摘要翻译： 反向交错型硅薄膜晶体管的制造方法包括在具有栅电极的基板上形成栅极绝缘层的步骤，栅极绝缘层具有晶体管形成部分; 在栅极绝缘层的晶体管形成部分上形成本征硅膜; 在本征硅层上形成n型硅层; 在n型硅层上形成源电极; 在n型硅层上形成漏电极; 在源电极和漏电极上形成抗蚀剂层并具有相同的形状; 然后通过使用抗蚀剂层作为掩模去除n型硅层的一部分，使得保留n型硅层的预定厚度; 并通过使用抗蚀剂层作为掩模，将p型杂质的n型硅层的预定厚度掺杂。

公开(公告)号：US5053354A

公开(公告)日：1991-10-01

申请号：US535440

申请日：1990-06-08

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L29/786

CPC分类号： H01L29/78669

摘要： A reverse staggered type silicon thin film transistor includes a substrate having a gate electrode; a gate insulating layer on the substrate and the gate electrode, the gate insulating layer having a transistor-forming portion; a lower layer silicon film on the transistor-forming portion of the gate insulating layer and in contact therewith, the lower layer silicon film being formed at a first temperature and with a first thickness; an upper layer silicon film formed on the transistor-forming portion of the gate insulating layer at a second temperature which is lower than the first temperature and with a second thickness greater than the first thickness; an n-type silicon layer on the upper layer silicon film and in contact therewith; a source electrode on the n-type silicon layer; and a drain electrode on the n-type silicon layer.

摘要翻译： 反向交错型硅薄膜晶体管包括具有栅电极的基板; 在所述基板上的栅极绝缘层和所述栅电极，所述栅极绝缘层具有晶体管形成部分; 在所述栅极绝缘层的所述晶体管形成部分上与其接触的下层硅膜，所述下层硅膜以第一温度和第一厚度形成; 在第二温度下形成在所述栅极绝缘层的所述晶体管形成部分上的上层硅膜，所述第二温度低于所述第一温度并且具有大于所述第一厚度的第二厚度; 在上层硅膜上并与其接触的n型硅层; n型硅层上的源电极; 和n型硅层上的漏电极。

公开(公告)号：US5122849A

公开(公告)日：1992-06-16

申请号：US564818

申请日：1990-08-08

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L29/786

CPC分类号： H01L29/78624 ,  H01L29/78618 ,  H01L29/78621

摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

摘要翻译： 硅薄膜晶体管阵列包括阵列状形式的多个硅薄膜晶体管，每个硅薄膜晶体管包括绝缘基板，形成在绝缘基板上的栅电极，形成在绝缘基板上的栅绝缘层， 栅电极，一对第一杂质含有在栅极绝缘层上形成的跨越栅电极的端部的硅层，形成在一对第一杂质上的本征硅层含有硅层和在 一对第一杂质之间的栅极绝缘层包含硅层，以便连接一对第一杂质含硅层，形成在本征硅层上的保护绝缘层，以及形成在源极电极和漏电极 该对第一杂质的接触部分含有硅层; 用于将硅薄膜晶体管的栅电极彼此连接的栅极布线; 以及用于将硅薄膜晶体管的源电极彼此连接的源极布线。

公开(公告)号：US5121178A

公开(公告)日：1992-06-09

申请号：US564816

申请日：1990-08-08

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/7866 ,  H01L29/78669

摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulating layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source wiring for connecting the source electrodes of the silicon thin film transistors to each other.

公开(公告)号：US5121177A

公开(公告)日：1992-06-09

申请号：US564806

申请日：1990-08-08

申请人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

发明人： Sakae Tanaka ,  Yoshiaki Watanabe ,  Katsuo Shirai ,  Yoshihisa Ogiwara

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/7866 ,  H01L29/78669

摘要： A silicon thin film transistor array includes a plurality of silicon thin film transistors in an array-like form, each silicon thin film transistor including an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating layer formed on the insulating substrate containing the gate electrode, a pair of first impurity contained silicon layers formed on the gate insulating layer in such a manner as to transversely cross a terminal part of the gate electrode, an intrinsic silicon layer formed on the pair of first impurity contained silicon layers and on the gate insulating layer between the pair of first impurity contained silicon layers in such a manner as to connect the pair of first impurity contained silicon layers, a protective insulation layer formed on the intrinsic silicon layer, and a source electrode and a drain electrode formed at contact parts of the pair of first impurity contained silicon layers; gate wiring for connecting the gate electrodes of the silicon thin film transistors to each other; and source writing for connecting the source electrodes of the silicon thin film transistors to each other.