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公开(公告)号：US07009535B2
公开(公告)日：2006-03-07
申请号：US11211506
申请日：2005-08-26
CPC分类号： B60T8/885 , B60T2270/402 , B62D5/0481 , G01D5/2073 , G05B9/02 , H03M1/1076 , H03M1/645
摘要： This resolver/digital converter has a resolver, a resolver/digital converting portion and an exciting signal generator. The exciting signal generated from the exciting signal generator is supplied to the resolver, and the resolver signals produced from the resolver are supplied to the resolver/digital converter. This resolver/digital converter further has a conversion trigger generator that generates a conversion trigger signal on the basis of the exciting signal generated from the exciting signal generator, an A/D converter that converts the resolver signals produced from the resolver to digital values in response to the conversion trigger signal generated from the conversion trigger generator, and computing means that detects the failure status on the basis of the digital values produced from the A/D converter.
摘要翻译： 该解算器/数字转换器具有分解器，分解器/数字转换部分和激励信号发生器。 从激励信号发生器产生的激励信号被提供给解算器，并且从分解器产生的解算器信号被提供给解算器/数字转换器。 该解算器/数字转换器还具有转换触发发生器，其基于从激励信号发生器产生的激励信号产生转换触发信号，A / D转换器将从分解器产生的分解器信号转换为数字值 涉及从转换触发发生器产生的转换触发信号，以及基于从A / D转换器产生的数字值来检测故障状态的计算装置。
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2.发明授权Phase detection circuit, resolver/digital converter using the circuit, and control system using the converter 有权相位检测电路，采用电路的解算器/数字转换器，以及使用转换器的控制系统公开(公告)号：US07456603B2
公开(公告)日：2008-11-25
申请号：US11488158
申请日：2006-07-18
IPC分类号： H02P23/00
CPC分类号： H03M1/485 , G01D5/2073
摘要： A small-sized and low-cost phase detection circuit which has improved noise immunity. The phase detection circuit comprises a multiplier for multiplying an input signal by a reference signal and outputting a first signal, an integration circuit for integrating the first signal and outputting a second signal, a phase estimation circuit for estimating phase information based on the second signal, and a reference signal generation circuit for generating the reference signal based on the estimated phase information. Since the phase is detected based on information representing an entire waveform, the influence of local noise can be diluted and noise immunity can be improved.
摘要翻译： 具有改进的抗噪声性能的小型和低成本的相位检测电路。 相位检测电路包括用于将输入信号乘以参考信号并输出第一信号的乘法器，用于积分第一信号并输出第二信号的积分电路，用于基于第二信号估计相位信息的相位估计电路， 以及参考信号生成电路，用于基于估计的相位信息产生参考信号。 由于基于表示整个波形的信息来检测相位，所以能够稀释局部噪声的影响，能够提高抗噪声性。
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3.发明申请Phase detection circuit, resolver/digital converter using the circuit, and control system using the converter 有权相位检测电路，采用电路的解算器/数字转换器，以及使用转换器的控制系统公开(公告)号：US20070029955A1
公开(公告)日：2007-02-08
申请号：US11488158
申请日：2006-07-18
IPC分类号： H02P7/32
CPC分类号： H03M1/485 , G01D5/2073
摘要： A small-sized and low-cost phase detection circuit which has improved noise immunity. The phase detection circuit comprises a multiplier for multiplying an input signal by a reference signal and outputting a first signal, an integration circuit for integrating the first signal and outputting a second signal, a phase estimation circuit for estimating phase information based on the second signal, and a reference signal generation circuit for generating the reference signal based on the estimated phase information. Since the phase is detected based on information representing an entire waveform, the influence of local noise can be diluted and noise immunity can be improved.
摘要翻译： 具有改进的抗噪声性能的小型和低成本的相位检测电路。 相位检测电路包括用于将输入信号乘以参考信号并输出第一信号的乘法器，用于积分第一信号并输出第二信号的积分电路，用于基于第二信号估计相位信息的相位估计电路， 以及参考信号生成电路，用于基于估计的相位信息产生参考信号。 由于基于表示整个波形的信息来检测相位，所以能够稀释局部噪声的影响，能够提高抗噪声性。
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公开(公告)号：US06972700B2
公开(公告)日：2005-12-06
申请号：US11043639
申请日：2005-01-27
IPC分类号： G01D5/244 , B60T8/88 , B60T17/18 , B62D5/04 , G01D5/20 , G05B9/02 , G05D3/12 , H03M1/10 , H03M1/64 , H03M1/00 , G05B1/06
CPC分类号： B60T8/885 , B60T2270/402 , B62D5/0481 , G01D5/2073 , G05B9/02 , H03M1/1076 , H03M1/645
摘要： This resolver/digital converter has a resolver, a resolver/digital converting portion and an exciting signal generator. The exciting signal generated from the exciting signal generator is supplied to the resolver, and the resolver signals produced from the resolver are supplied to the resolver/digital converter. This resolver/digital converter further has a conversion trigger generator that generates a conversion trigger signal on the basis of the exciting signal generated from the exciting signal generator, an A/D converter that converts the resolver signals produced from the resolver to digital values in response to the conversion trigger signal generated from the conversion trigger generator, and computing means that detects the failure status on the basis of the digital values produced from the A/D converter.
摘要翻译： 该解算器/数字转换器具有分解器，分解器/数字转换部分和激励信号发生器。 从激励信号发生器产生的激励信号被提供给解算器，并且从分解器产生的解算器信号被提供给解算器/数字转换器。 该解算器/数字转换器还具有转换触发发生器，其基于从激励信号发生器产生的激励信号产生转换触发信号，A / D转换器将从分解器产生的分解器信号转换为数字值 涉及从转换触发发生器产生的转换触发信号，以及基于从A / D转换器产生的数字值来检测故障状态的计算装置。
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公开(公告)号：US20050280570A1
公开(公告)日：2005-12-22
申请号：US11211506
申请日：2005-08-26
IPC分类号： G01D5/244 , B60T8/88 , B60T17/18 , B62D5/04 , G01D5/20 , G05B9/02 , G05D3/12 , H03M1/10 , H03M1/64 , H03M1/12
CPC分类号： B60T8/885 , B60T2270/402 , B62D5/0481 , G01D5/2073 , G05B9/02 , H03M1/1076 , H03M1/645
摘要： This resolver/digital converter has a resolver, a resolver/digital converting portion and an exciting signal generator. The exciting signal generated from the exciting signal generator is supplied to the resolver, and the resolver signals produced from the resolver are supplied to the resolver/digital converter. This resolver/digital converter further has a conversion trigger generator that generates a conversion trigger signal on the basis of the exciting signal generated from the exciting signal generator, an A/D converter that converts the resolver signals produced from the resolver to digital values in response to the conversion trigger signal generated from the conversion trigger generator, and computing means that detects the failure status on the basis of the digital values produced from the A/D converter.
摘要翻译： 该解算器/数字转换器具有分解器，分解器/数字转换部分和激励信号发生器。 从激励信号发生器产生的激励信号被提供给解算器，并且从分解器产生的解算器信号被提供给解算器/数字转换器。 该解算器/数字转换器还具有转换触发发生器，其基于从激励信号发生器产生的激励信号产生转换触发信号，A / D转换器将从分解器产生的分解器信号转换为数字值 涉及从转换触发发生器产生的转换触发信号，以及基于从A / D转换器产生的数字值来检测故障状态的计算装置。
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公开(公告)号：US20050162292A1
公开(公告)日：2005-07-28
申请号：US11043639
申请日：2005-01-27
IPC分类号： G01D5/244 , B60T8/88 , B60T17/18 , B62D5/04 , G01D5/20 , G05B9/02 , G05D3/12 , H03M1/10 , H03M1/64 , H03M1/48
CPC分类号： B60T8/885 , B60T2270/402 , B62D5/0481 , G01D5/2073 , G05B9/02 , H03M1/1076 , H03M1/645
摘要： This resolver/digital converter has a resolver, a resolver/digital converting portion and an exciting signal generator. The exciting signal generated from the exciting signal generator is supplied to the resolver, and the resolver signals produced from the resolver are supplied to the resolver/digital converter. This resolver/digital converter further has a conversion trigger generator that generates a conversion trigger signal on the basis of the exciting signal generated from the exciting signal generator, an A/D converter that converts the resolver signals produced from the resolver to digital values in response to the conversion trigger signal generated from the conversion trigger generator, and computing means that detects the failure status on the basis of the digital values produced from the A/D converter.
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7.发明授权公开(公告)号：US07969229B2
公开(公告)日：2011-06-28
申请号：US12389194
申请日：2009-02-19
IPC分类号： G06F11/16
CPC分类号： G06F11/1645 , G06F11/1641 , G06F11/165
摘要： A comparator circuit for comparing outputs of an on-chip redundant system is mounted on a second semiconductor chip that is separate from the on-chip redundant system. The second semiconductor chip which preferably contains a power source circuit for supplying power to the on-chip redundant system, a driver circuit for driving an output circuit, and the like are mounted. With this configuration, the influence of a failure occurring in the on-chip redundancy system can be prevented from being exerted on the comparator measure.
摘要翻译： 用于比较片上冗余系统的输出的比较器电路安装在与片上冗余系统分离的第二半导体芯片上。 优选地，包含用于向片上冗余系统供电的电源电路的第二半导体芯片，用于驱动输出电路的驱动电路等。 利用这种配置，可以防止在片上冗余系统中发生的故障对比较器测量的影响。
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8.发明申请公开(公告)号：US20100207681A1
公开(公告)日：2010-08-19
申请号：US12389194
申请日：2009-02-19
IPC分类号： G06F11/16
CPC分类号： G06F11/1645 , G06F11/1641 , G06F11/165
摘要： The present invention is directed to improve reliably of an on-chip redundancy system by preventing influence of a physical failure exerted on an entire semiconductor chip. A comparator measure for comparing outputs of an on-chip redundancy system is mounted on a semiconductor chip different from the on-chip redundancy system. The another semiconductor chip is, preferably, mounted on a semiconductor chip on which a power source circuit for supplying power to the on-chip redundancy system redundantly having the comparing function in the chip, a driver circuit for driving an output circuit, and the like are mounted. With the configuration, the influence of a failure occurring in the on-chip redundancy system can be prevented from being exerted on the comparator measure.
摘要翻译： 本发明旨在通过防止对整个半导体芯片施加的物理故障的影响来可靠地提高片上冗余系统。 用于比较片上冗余系统的输出的比较器测量装置安装在不同于片上冗余系统的半导体芯片上。 另一半导体芯片优选地安装在半导体芯片上，在半导体芯片上，用于向片上冗余系统供电的电源电路冗余地具有芯片中的比较功能，用于驱动输出电路的驱动电路等 被安装。 利用该配置，可以防止在片上冗余系统中发生的故障的影响施加在比较器测量上。
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9.发明申请Communication System, Real-Time Control Device, and Information Processing System 有权通信系统，实时控制设备和信息处理系统公开(公告)号：US20090022255A1
公开(公告)日：2009-01-22
申请号：US10578188
申请日：2004-10-01
申请人： Nobuyasu Kanekawa , Shoji Sasaki , Takanori Yokoyama , Kunihiko Tsunedomi , Junji Miyake , Katsuya Oyama
发明人： Nobuyasu Kanekawa , Shoji Sasaki , Takanori Yokoyama , Kunihiko Tsunedomi , Junji Miyake , Katsuya Oyama
IPC分类号： H04L7/00
CPC分类号： G06F13/4291
摘要： In addition to fast on-off timing, instructive information on an output wave such as an amplitude or a slope is transmitted through a small number of signal lines. Output wave modifier information such as the amplitude or slope is transferred through serial communication 1, and an on-off timing signal is transmitted as an individual signal 20.
摘要翻译： 除了快速开关定时之外，通过少量的信号线发送诸如振幅或斜率的输出波的指导信息。 诸如幅度或斜率的输出波修正器信息通过串行通信1传送，并且开 - 关定时信号作为单独信号20发送。
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10.发明授权Communication system, real-time control device, and information processing system 有权通讯系统，实时控制装置及信息处理系统公开(公告)号：US07680228B2
公开(公告)日：2010-03-16
申请号：US10578188
申请日：2004-10-01
申请人： Nobuyasu Kanekawa , Shoji Sasaki , Takanori Yokoyama , Kunihiko Tsunedomi , Junji Miyake , Katsuya Oyama
发明人： Nobuyasu Kanekawa , Shoji Sasaki , Takanori Yokoyama , Kunihiko Tsunedomi , Junji Miyake , Katsuya Oyama
IPC分类号： H04L7/02
CPC分类号： G06F13/4291
摘要： In addition to fast on-off timing, instructive information on an output wave such as an amplitude or a slope is transmitted through a small number of signal lines. Output wave modifier information such as the amplitude or slope is transferred through serial communication 1, and an on-off timing signal is transmitted as an individual signal 20.
摘要翻译： 除了快速开关定时之外，通过少量的信号线发送诸如振幅或斜率的输出波的指导信息。 诸如幅度或斜率的输出波修正器信息通过串行通信1传送，并且开 - 关定时信号作为单独信号20发送。
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