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公开(公告)号：US20070262353A1
公开(公告)日：2007-11-15
申请号：US11790517
申请日：2007-04-26
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78687
摘要： A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.
摘要翻译： 根据本发明的实施例的半导体器件包括：由形成在衬底上并被四个侧面包围的第一半导体层制成的方形极形沟道部分; 形成在所述沟道部分的第一侧面上的栅极电极和通过各个栅极绝缘膜的所述沟道部分与所述第一侧面相对的第二侧面; 源极区，其具有不同于沟道部分的导电类型并形成在沟道部分的第三侧面上的源极区，源极区包括具有与第一半导体层的晶格常数不同的晶格常数的第二半导体层，并形成 直接在基材上; 以及漏极区，其具有与沟道部分不同的导电类型，并且形成在与第三侧面相对的沟道部分的第四侧面上，包括第二半导体层的漏极区域直接形成在衬底上。
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2.发明授权Semiconductor device having a pole-shaped portion and method of fabricating the same 失效具有极形部分的半导体器件及其制造方法公开(公告)号：US07683436B2
公开(公告)日：2010-03-23
申请号：US11790517
申请日：2007-04-26
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78687
摘要： A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.
摘要翻译： 根据本发明的实施例的半导体器件包括：由形成在衬底上并被四个侧面包围的第一半导体层制成的方形极形沟道部分; 形成在所述沟道部分的第一侧面上的栅极电极和通过各个栅极绝缘膜的所述沟道部分与所述第一侧面相对的第二侧面; 源极区，其具有不同于沟道部分的导电类型并形成在沟道部分的第三侧面上的源极区，源极区包括具有与第一半导体层的晶格常数不同的晶格常数的第二半导体层，并形成 直接在基材上; 以及漏极区，其具有与沟道部分不同的导电类型，并且形成在与第三侧面相对的沟道部分的第四侧面上，包括第二半导体层的漏极区域直接形成在衬底上。
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公开(公告)号：US20100151645A1
公开(公告)日：2010-06-17
申请号：US12656767
申请日：2010-02-16
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78687
摘要： A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.
摘要翻译： 根据本发明的实施例的半导体器件包括：由形成在衬底上并被四个侧面包围的第一半导体层制成的方形极形沟道部分; 形成在所述沟道部分的第一侧面上的栅极电极和通过各个栅极绝缘膜的所述沟道部分与所述第一侧面相对的第二侧面; 源极区，其具有不同于沟道部分的导电类型并形成在沟道部分的第三侧面上的源极区，源极区包括具有与第一半导体层的晶格常数不同的晶格常数的第二半导体层，并形成 直接在基材上; 以及漏极区，其具有与沟道部分不同的导电类型，并且形成在与第三侧面相对的沟道部分的第四侧面上，包括第二半导体层的漏极区域直接形成在衬底上。
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公开(公告)号：US08062938B2
公开(公告)日：2011-11-22
申请号：US12656767
申请日：2010-02-16
IPC分类号： H01L21/00
CPC分类号： H01L29/785 , H01L29/66818 , H01L29/78687
摘要： A semiconductor device according to an embodiment of the present invention includes: a square pole-shaped channel portion made from a first semiconductor layer formed on a substrate, and surrounded with four side faces; a gate electrode formed on a first side face of the channel portion, and a second side face of the channel portion opposite to the first side face through respective gate insulating films; a source region having a conductivity type different from that of the channel portion and being formed on a third side face of the channel portion, the source region including a second semiconductor layer having a lattice constant different from that of the first semiconductor layer and being formed directly on the substrate; and a drain region having a conductivity type different from that of the channel portion and being formed on a fourth side face of the channel portion opposite to the third side face, the drain region including the second semiconductor layer being formed directly on the substrate.
摘要翻译： 根据本发明的实施例的半导体器件包括：由形成在衬底上并被四个侧面包围的第一半导体层制成的方形极形沟道部分; 形成在所述沟道部分的第一侧面上的栅极电极和通过各个栅极绝缘膜的所述沟道部分与所述第一侧面相对的第二侧面; 源极区，其具有不同于沟道部分的导电类型并形成在沟道部分的第三侧面上的源极区，源极区包括具有与第一半导体层的晶格常数不同的晶格常数的第二半导体层，并形成 直接在基材上; 以及漏极区，其具有与沟道部分不同的导电类型，并且形成在与第三侧面相对的沟道部分的第四侧面上，包括第二半导体层的漏极区域直接形成在衬底上。
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5.发明授权公开(公告)号：US08648404B2
公开(公告)日：2014-02-11
申请号：US13298664
申请日：2011-11-17
申请人： Nikka Ko , Katsunori Yahashi
发明人： Nikka Ko , Katsunori Yahashi
IPC分类号： H01L29/792 , H01L21/8247
CPC分类号： H01L27/11556 , H01L27/0688 , H01L27/11548 , H01L27/11575 , H01L27/11582
摘要： A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.
摘要翻译： 三维半导体器件包括半导体衬底，多个导电层和绝缘层以及多个触点。 多个导电层和绝缘层交替堆叠在半导体衬底上。 多个触点在多个导电层和绝缘层的层叠方向上延伸。 多个导电层形成阶梯部，该多个导电层的端部的位置从上层向下层逐渐移动。 多个触点分别连接到阶梯部分的每个台阶。 台阶部分形成为使得至少从最上层的导电层到某一导电层，导电层位于更上方，台阶的宽度越宽。
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公开(公告)号：US08216942B2
公开(公告)日：2012-07-10
申请号：US12274076
申请日：2008-11-19
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139
摘要： A method for manufacturing a semiconductor device, comprises forming a first film above a pattern forming material, patterning the first film to form a core material pattern, forming a second film above the pattern forming material so as to cover a side surface and an upper surface of the core material pattern, forming a third film above the second film as a protective material for the second film, etching the second and third films so that side wall sections including the second film and the third film are formed on both sides of the core material pattern and the second film and the third film of an area other than the side wall sections are removed, removing the core material pattern between the side wall sections, and transferring patterns corresponding to the side wall sections on the pattern forming material by using the side wall sections as a mask.
摘要翻译： 一种制造半导体器件的方法，包括在图案形成材料上形成第一膜，图案化第一膜以形成芯材图案，在图案形成材料上形成第二膜以覆盖侧表面和上表面 的芯材图案，在第二膜上形成第三膜作为第二膜的保护材料，蚀刻第二和第三膜，使得包括第二膜和第三膜的侧壁部分形成在芯的两侧 去除除了侧壁部分之外的区域的第二膜和第二膜，除去侧壁部分之间的芯材图案，并且通过使用图案形成材料将对应于侧壁部分的图案转移到图案形成材料上 侧壁部分作为掩模。
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7.发明授权公开(公告)号：US07939891B2
公开(公告)日：2011-05-10
申请号：US12409092
申请日：2009-03-23
IPC分类号： H01L27/12
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, filled in portions separated from the sidewalls, having upper portions higher than the surface of the substrate and having silicide layers formed on regions of exposed from the substrate. The lower portion of the SiGe film that faces the electrode is formed to extend in a direction perpendicular to the surface of the substrate and the upper portion is inclined and separated farther apart from the gate electrode as the upper portion is separated away from the surface of the substrate. The surface of the silicide layer of the SiGe film that faces the gate electrode is higher than the channel region.
摘要翻译： 半导体器件包括层叠在基板上的电介质膜和栅电极，形成为覆盖电极和电介质膜的侧面的侧壁和形成为夹持侧壁，电极和电介质膜的SiGe膜，填充有与 所述侧壁具有高于所述基板的表面的上部，并且在从所述基板暴露的区域上形成有硅化物层。 SiGe膜的与电极相对的下部形成为在垂直于基板的表面的方向上延伸，并且当上部与栅电极的表面分离时，上部分与栅电极分离得更远离， 底物。 面向栅电极的SiGe膜的硅化物层的表面高于沟道区。
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公开(公告)号：US20090221147A1
公开(公告)日：2009-09-03
申请号：US12395094
申请日：2009-02-27
IPC分类号： H01L21/306
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139 , Y10S438/947
摘要： A method of fabricating a semiconductor device according to an embodiment includes: forming a core material on a workpiece material; forming a cover film to cover the upper and side surfaces of the core material; after forming the cover film, removing the core material; after removing the core material, removing the cover film while leaving portions thereof located on the side surfaces of the core material, so as to form sidewall spacer masks; and etching the workpiece material by using the sidewall spacer masks as a mask.
摘要翻译： 根据实施例的制造半导体器件的方法包括：在工件材料上形成芯材; 形成覆盖所述芯材的上表面和侧表面的覆盖膜; 在形成覆盖膜之后，去除芯材; 在去除芯材之后，移除覆盖膜，同时留下位于芯材侧表面的部分，以便形成侧壁间隔物掩模; 并且通过使用侧壁间隔物掩模作为掩模来蚀刻工件材料。
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公开(公告)号：US20090212337A1
公开(公告)日：2009-08-27
申请号：US12388667
申请日：2009-02-19
IPC分类号： H01L31/112 , H01L21/762
CPC分类号： H01L27/1463 , H01L21/76229 , H01L21/823481 , H01L27/14689
摘要： A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate.
摘要翻译： 在半导体基板上形成硬掩模材料膜，并且在半导体基板的上表面的开口的正下方形成凹部。 接下来，使用硬掩模材料膜作为掩模，通过将杂质注入成像区域而在凹部的正下方形成p型区域。 此外，通过在处理区域中进一步处理凹部来形成沟槽。 通过在凹槽和沟槽中埋入介电材料以除去硬掩模材料膜来形成半埋电介质膜和STI。 接下来，形成两个电极，以分别与半埋电介质膜和STI重叠，并且使用一个电极和半埋电介质膜作为掩模将杂质注入到成像区域中，因此n型 构成光电二极管的区域形成在与半导体衬底中的p型区域接触的区域中。
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10.发明授权Semiconductor device manufacturing method including exposing electrode layers into a hole 有权半导体器件制造方法，包括将电极层暴露于孔中公开(公告)号：US08273628B2
公开(公告)日：2012-09-25
申请号：US12718641
申请日：2010-03-05
申请人： Katsunori Yahashi
发明人： Katsunori Yahashi
IPC分类号： H01L21/336
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A semiconductor device manufacturing method includes: alternately stacking a plurality of insulating layers and electrode layers; forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers; forming a conductive film on an inner wall of the hole; anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole; altering the conductive film into an insulator by heat treatment; and removing the insulator covering the electrode layers to expose the electrode layers into the hole.
摘要翻译： 半导体器件制造方法包括：交替堆叠多个绝缘层和电极层; 形成穿过绝缘层和电极层的多层体的孔; 在孔的内壁上形成导电膜; 各向异性地蚀刻导电膜以选择性地将导电膜留在孔的侧壁上; 通过热处理将导电膜改变成绝缘体; 并且去除覆盖电极层的绝缘体，以将电极层暴露于孔中。
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