公开(公告)号：US09384053B2

公开(公告)日：2016-07-05

申请号：US13880575

申请日：2011-05-31

申请人： Noriaki Suzuki

发明人： Noriaki Suzuki

IPC分类号： G06F9/46 ,  G06F9/50

CPC分类号： G06F9/5027 ,  G06F9/50 ,  G06F9/5066

摘要： A state evaluation function value generation unit 131 generates a state evaluation function value for each operating state based on a state/task-set correspondence table indicating a list of an operating state of a system including a plurality of processor-cores and correspondence of a task set to be operated in each operating state, and a task set parameter indicating a characteristic of each task constituting the task set. An integrated evaluation function value generation unit 132 generates an integrated evaluation function value in which the state evaluation function value of each operating state is integrated. An optimal allocation search unit 133 optimizes allocation of a task to be allocated to each of the plurality of processor-cores based on the integrated evaluation function value.

摘要翻译： 状态评价函数值生成部131基于表示包括多个处理器核心的系统的运行状态的列表的状态/任务集对应表以及任务的对应关系来生成各运行状态的状态评价函数值 设置为在每个操作状态下操作，以及指示构成任务集的每个任务的特征的任务设置参数。 集成评价函数值生成部132生成各运算状态的状态评价函数值一体化的综合评价函数值。 最优分配搜索单元133基于综合评估函数值优化要分配给多个处理器核心中的每一个的任务的分配。

公开(公告)号：US08738881B2

公开(公告)日：2014-05-27

申请号：US12865781

申请日：2009-02-06

申请人： Noriaki Suzuki ,  Sunao Torii ,  Junji Sakai

发明人： Noriaki Suzuki ,  Sunao Torii ,  Junji Sakai

IPC分类号： G06F12/08 ,  G06F3/06

CPC分类号： G06F3/0644 ,  G06F11/3419 ,  G06F11/3466 ,  G06F12/0802 ,  G06F2201/88 ,  G06F2201/885

摘要： Provided is a performance optimization system that can identify a case where the impact on performance is large even when the number of cache misses is small. The performance optimization system includes: a required-period-of-time measurement unit that measures a required period of time concerning a to-be-observed access; a required-period-of-time table holding unit that holds a required-period-of-time table that consists of a plurality of table entries in which stored are measured values of the required period of time for each of classification regions produced by dividing a memory region for each of types based on the to-be-observed access to store a measured value of the required period of time; a table entry selection unit that makes a selection as to in which table entry, out of a plurality of table entries for each of the classification regions that make up the required-period-of-time table, the measured value of the required period of time is stored on the basis of the to-be-observed access; and a cache miss observation unit that detects the occurrence of a cache miss associated with the to-be-observed access.

摘要翻译： 提供了一种性能优化系统，可以识别即使高速缓存未命中的数量较小，对性能的影响也很大的情况。 绩效优化系统包括：一个需要的时间测量单元，用于测量与待观察的访问有关的所需时间; 所需时间表保持单元，其保存由存储的多个表条目组成的所需时间周期表，所述时间表存储的是通过划分产生的每个分类区域所需的时间段的测量值 基于待观察访问的每种类型的存储区域来存储所需时间段的测量值; 表格条目选择单元，对于构成所需时间表的每个分类区域的多个表条目中的哪个表条目进行选择所需时间段的测量值 时间根据被观察的访问存储; 以及高速缓存未命中观察单元，其检测与所述待观察访问相关联的高速缓存未命中的发生。

公开(公告)号：US08387095B2

公开(公告)日：2013-02-26

申请号：US12748716

申请日：2010-03-29

申请人： Takashi Ohki ,  Noriaki Suzuki

发明人： Takashi Ohki ,  Noriaki Suzuki

IPC分类号： H04N7/173 ,  H04N7/14 ,  G08C19/00 ,  H04N7/10 ,  H04Q1/00

CPC分类号： H04N7/17318 ,  H04H60/73 ,  H04H2201/40 ,  H04N5/44543 ,  H04N21/4348 ,  H04N21/44227 ,  H04N21/4586 ,  H04N21/4622 ,  H04N21/482 ,  H04N21/84

摘要： A broadcast receiving apparatus includes a determination unit that determines whether an external apparatus is capable of transmitting broadcast program information about a plurality of channels via a communication unit. When the determination unit determines that the external apparatus is capable of transmitting the broadcast program information, an acquisition unit does not acquire the broadcast program information from the digital broadcast signal. The external apparatus is requested to transmit the broadcast program information. The broadcast program information is acquired from the external apparatus.

摘要翻译： 广播接收装置包括确定单元，其确定外部设备是否能够经由通信单元发送关于多个信道的广播节目信息。 当确定单元确定外部设备能够发送广播节目信息时，获取单元不从数字广播信号获取广播节目信息。 请求外部设备发送广播节目信息。 从外部装置获取广播节目信息。

公开(公告)号：US07911216B2

公开(公告)日：2011-03-22

申请号：US12525953

申请日：2008-01-25

申请人： Noriaki Suzuki ,  Sunao Torii

发明人： Noriaki Suzuki ,  Sunao Torii

IPC分类号： G01R31/3187

CPC分类号： G06F11/3636 ,  G06F11/3648

摘要： A main functional structure executes continuous predetermined operations to continuously generate events associated with the operations. A debug/trace circuit compares an event occurring at the main functional structure with detection condition indicating information of one entry in a control information list, and executes the operation designated by operation indicating information paired with the detection condition indicating information in accordance with the result of the comparison. The debug/trace circuit continuously performs this in accordance with the control information list to identify the event.

摘要翻译： 主要功能结构执行连续的预定操作，以连续地生成与操作有关的事件。 调试/跟踪电路将主功能结构中发生的事件与指示控制信息列表中的一个条目的信息的检测条件进行比较，并且根据检测条件指示信息的结果执行与指示信息配对的操作指定的操作 比较。 调试/跟踪电路根据控制信息列表连续执行此操作以识别事件。

公开(公告)号：US6118699A

公开(公告)日：2000-09-12

申请号：US352838

申请日：1999-07-13

申请人： Yuuichi Tatsumi ,  Noriaki Suzuki ,  Hidenobu Minagawa ,  Kazuhiko Satou ,  Hitoshi Ohta

发明人： Yuuichi Tatsumi ,  Noriaki Suzuki ,  Hidenobu Minagawa ,  Kazuhiko Satou ,  Hitoshi Ohta

IPC分类号： H01L27/115 ,  G11C16/04

CPC分类号： G11C16/0416 ,  H01L27/115

摘要： That surface portion of a semiconductor substrate which is adjacent to a buried source region formed in the substrate is covered with an offset side wall to suppress expansion of a channel beneath the offset side wall. In addition, buried source regions in the form of offset side walls are formed on the two sides of a drain region having one non-offset side wall to prevent a write or read error in unselected memory cell transistors on both sides of a selected memory transistor either in a data write or in a data read.

摘要翻译： 与形成在基板中的埋入源极区域相邻的半导体基板的表面部分被偏移侧壁覆盖，以抑制偏移侧壁下方的通道的膨胀。 此外，在具有一个非偏移侧壁的漏极区域的两侧上形成有偏移侧壁形式的掩埋源极区域，以防止选定存储晶体管两侧的未选择的存储单元晶体管中的写入或读取错误 在数据写入或数据读取中。

公开(公告)号：US5538044A

公开(公告)日：1996-07-23

申请号：US539162

申请日：1995-10-04

申请人： Motofumi Koyuba ,  Naoki Konno ,  Noriaki Suzuki

发明人： Motofumi Koyuba ,  Naoki Konno ,  Noriaki Suzuki

IPC分类号： B32B15/01 ,  F16L11/16

CPC分类号： B32B15/011 ,  Y10S138/06 ,  Y10T428/12

摘要： Welded steel pipe having wear resistance properties, corrosion resistance and low-temperature toughness is provided by preparing welded steel pipe formed of composite steel material comprised of an outer layer of high-carbon, low-alloy steel and an inner layer having a relatively low carbon content, heating the pipe to a temperature that is not less than 800.degree. C. and not more than 900.degree. C. and then quenching the pipe so as to harden just the high-carbon outer layer, and if necessary this can be followed by reheating at a temperature of not less than 200.degree. C. and not more than 600.degree. C. to thereby produce a pipe with an inner layer having high corrosion resistance and low temperature toughness and an outer layer having high hardness.

摘要翻译： 具有耐磨性，耐腐蚀性和低温韧性的焊接钢管通过制备由包含高碳，低合金钢外层和碳含量较低的内层的复合钢材制成的焊接钢管 将管道加热到不低于800℃并且不超过900℃的温度，然后淬火管道，以便仅硬化高碳外层，如果需要，可以随后 在不低于200℃且不超过600℃的温度下再加热，从而制得具有高耐腐蚀性和低温韧性的内层的管和具有高硬度的外层。

公开(公告)号：US5023839A

公开(公告)日：1991-06-11

申请号：US551330

申请日：1990-07-12

申请人： Noriaki Suzuki ,  Junichi Miyamoto ,  Nobuaki Ohtsuka

发明人： Noriaki Suzuki ,  Junichi Miyamoto ,  Nobuaki Ohtsuka

IPC分类号： G11C17/00 ,  G06F11/00 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/78 ,  G06F11/00 ,  G11C16/28

摘要： An improved semiconductor memory device having a memory array, a dummy cell and a redundancy cell column is disclosed. At least one dummy capacity cell is connected to the reference bit line to which the dummy cell is connected, and also to a redundancy bit line to which redundancy cells are connected. Therefore, since a capacity on the reference bit line is roughly equalized to that on the redundancy bit line by these dummy capacity cells, it is possible to prevent erroneous potential level determination by a sense amplifier for comparing both the potentials on both the bit lines, without being subjected to the influence of supply voltage fluctuations.

公开(公告)号：US08881158B2

公开(公告)日：2014-11-04

申请号：US13063232

申请日：2009-08-20

申请人： Noriaki Suzuki ,  Junji Sakai

发明人： Noriaki Suzuki ,  Junji Sakai

IPC分类号： G06F9/46 ,  G06F9/50

CPC分类号： G06F9/5038 ,  G06F2209/5017 ,  G06F2209/506

摘要： A schedule decision method acquires dependencies of execution sequences required for a plurality of sub tasks into which a first task has been divided; generates a plurality of sub task structure candidates that satisfy said dependencies and for which a plurality of processing devices execute said plurality of sub tasks; generates a plurality of schedule candidates by further assigning at least one second task to each of said sub task structure candidates; computes an effective degree that represents effectiveness of executions of said first task and said second task for each of said plurality of schedule candidates; and decides a schedule candidate used for the executions of said first task and said second task from said plurality of schedule candidates based on said effective degrees.

摘要翻译： 时间表决定方法获取第一任务被划分到的多个子任务所需的执行序列的依赖关系; 生成满足所述依赖性的多个子任务结构候选，并且多个处理装置执行所述多个子任务; 通过对每个所述子任务结构候选进一步分配至少一个第二任务来生成多个调度候选; 计算表示对于所述多个日程表候选中的每一个的所述第一任务和所述第二任务的执行的有效性的有效程度; 并且基于所述有效度，从所述多个日程表候选中确定用于执行所述第一任务和所述第二任务的日程表候选。

公开(公告)号：US08799753B2

公开(公告)日：2014-08-05

申请号：US12863934

申请日：2009-02-03

申请人： Noriaki Suzuki ,  Junji Sakai

发明人： Noriaki Suzuki ,  Junji Sakai

IPC分类号： G06F7/02 ,  G06F11/00 ,  G06F11/36

CPC分类号： G06F11/3636 ,  G06F11/3648

摘要： There is provided a trace/failure observation system which is capable of comprehensive collection of information that is needed for checking a desired operation in a system or the like where the amount of information to be observed is large, and which allows easy analysis of the desired operation. The system includes, in a system LSI to be subjected to trace/failure observation: an event detecting means for observing behavior of a portion to be observed; a first data reducing means for performing observation data reduction processing so that observation data from the event detecting means has an amount of information processable to a second data reducing means; and the second data reducing means for performing one or more steps of observation data reduction processing.

摘要翻译： 提供了一种跟踪/故障观察系统，其能够综合地收集在要观察的信息量大的系统等中检查所需操作所需的信息，并且允许容易地分析所需的 操作。 该系统包括在要进行跟踪/故障观察的系统LSI中：事件检测装置，用于观察待观察部分的行为; 第一数据减少装置，用于执行观察数据缩减处理，使得来自事件检测装置的观察数据具有可处理到第二数据减少装置的信息量; 以及用于执行观察数据缩减处理的一个或多个步骤的第二数据减少装置。

公开(公告)号：US20130055181A1

公开(公告)日：2013-02-28

申请号：US13643604

申请日：2011-04-26

申请人： Noriaki Suzuki

发明人： Noriaki Suzuki

IPC分类号： G06F17/50

CPC分类号： G06F17/5027 ,  G06F11/261 ,  G06F17/5022 ,  G06F17/5054 ,  H03K19/17744

摘要： A logic circuit emulator comprises multiple sub-systems, in which each sub-system outputs to another one of the sub-systems a permission notification to permit the another sub-system to proceed to next emulation clock cycle depending on whether or not the state of an own sub-circuit has advanced. In case a signal that is output from an own sub-circuit and that is to be sent to a sub-circuit of the other sub-system has changed, each sub-system outputs a transfer request to transfer the signal to the another sub-system before the next emulation clock cycle. In case a signal is not being sent from the own sub-circuit to the sub-circuit of the another sub-system, and a permission notification is received but no transfer request is being received from the other sub-system, a clock signal is output for the own sub-circuit to advance the own sub-circuit to the next emulation clock cycle.

摘要翻译： 逻辑电路仿真器包括多个子系统，其中每个子系统向另一个子系统输出许可通知，允许另一个子系统进行下一个仿真时钟周期，这取决于是否有 自己的子电路已经进步了。 在从自己的子电路输出并且要发送到另一子系统的子电路的信号已经改变的情况下，每个子系统输出传送请求以将信号传送到另一个子系统， 系统在下一个仿真时钟周期之前。 在没有从自己的子电路向另一子系统的子电路发送信号的情况下，接收到许可通知但没有从其他子系统接收到转移请求的情况下，时钟信号为 输出自己的子电路，将自己的子电路推进到下一个仿真时钟周期。