公开(公告)号：US20060181325A1

公开(公告)日：2006-08-17

申请号：US11055824

申请日：2005-02-11

申请人： Norman James ,  Brian Monwai

发明人： Norman James ,  Brian Monwai

IPC分类号： G06F1/04

CPC分类号： G11C29/02 ,  G01R31/31727 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/50012

摘要： A system and method for performing functional verification of a device, and in particular a technique for performing phase-locked loop (PLL) functional verification by the device which contains the PLL circuitry. A relatively slow-speed external clock is provided to the device, and is used to generate control signals to a counter. PLL circuitry within the device generates a relatively high-speed master clock signal for use by the device. This master clock signal is coupled to a clock input of the counter, the counter having various control inputs that are used to selectively count clock pulses of the master clock. As the frequency of the external clock signal is known, and the master clock signal is generated from known PLL circuitry, it is possible to analyze the count value from the counter to determine whether the PLL circuitry used to generate the master clock is operating properly.

摘要翻译： 用于执行设备的功能验证的系统和方法，特别是用于由包含PLL电路的设备进行锁相环（PLL）功能验证的技术。 相对较慢的外部时钟提供给设备，并用于产生控制信号到计数器。 器件内的PLL电路产生相对高速的主时钟信号供设备使用。 该主时钟信号耦合到计数器的时钟输入端，该计数器具有用于选择性地对主时钟的时钟脉冲进行计数的各种控制输入。 由于外部时钟信号的频率是已知的，并且主时钟信号是从已知的PLL电路产生的，所以可以从计数器分析计数值，以确定用于产生主时钟的PLL电路是否正常工作。

公开(公告)号：US20060179184A1

公开(公告)日：2006-08-10

申请号：US11055675

申请日：2005-02-10

申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

IPC分类号： G06F3/06 ,  G06F3/02 ,  G06F3/00

CPC分类号： G06F15/161

摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

公开(公告)号：US20060176897A1

公开(公告)日：2006-08-10

申请号：US11055404

申请日：2005-02-10

申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

IPC分类号： H04L12/66

CPC分类号： G06F15/7842

摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 Fabric命令转换为FSI协议，并转发到附加的支持芯片以访问内存映射资源，并将来自支持芯片的响应转换回Fabric响应数据包。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。

公开(公告)号：US20060176049A1

公开(公告)日：2006-08-10

申请号：US11055045

申请日：2005-02-10

申请人： Carl Anderson ,  Michael Floyd ,  Brian Monwai

发明人： Carl Anderson ,  Michael Floyd ,  Brian Monwai

IPC分类号： G01R31/28

CPC分类号： G06F11/24

摘要： A method and system for dynamic characterization observability using functional clocks for system or run-time process characterization. Silicon characterization circuitry may be read after silicon chips have been assembled in a package and installed in a system. A characterization circuit comprising one or more oscillators generates signal pulses, wherein the signal pulses represent a frequency of a circuit in the processor chip. A sampler circuit is connected to the characterization circuit, wherein the sampler circuit counts the number of the signal pulses from the characterization circuit within a predetermined time period. A control unit is connected to the sampler circuit, wherein the control unit comprises macros for collecting count data from the one or more oscillators to determine the silicon characterization. Based on the silicon characterization, the optimal operating frequency of the processor chip may be identified, as well as possible lifetime degradation of circuits on the chip.

摘要翻译： 使用功能时钟进行系统或运行时过程表征的动态表征可观察性的方法和系统。 硅片表征电路可以在硅芯片组装在封装中并安装在系统中之后被读取。 包括一个或多个振荡器的表征电路产生信号脉冲，其中信号脉冲表示处理器芯片中的电路的频率。 采样器电路连接到表征电路，其中采样器电路在预定时间段内对来自表征电路的信号脉冲的数量进行计数。 控制单元连接到采样器电路，其中控制单元包括用于收集来自一个或多个振荡器的计数数据的宏，以确定硅表征。 基于硅表征，可以识别处理器芯片的最佳工作频率，以及芯片上电路的可能的寿命衰退。