公开(公告)号：US09229053B2

公开(公告)日：2016-01-05

申请号：US14165871

申请日：2014-01-28

Applicant: Nvidia Corporation

Inventor： Padam Krishnani ,  Supreet Agrawal ,  Kwanjee Ng

IPC: G01R31/317 ,  G06F1/32 ,  G06F1/26

CPC classification number: G01R31/31705 ,  G01R31/31721 ,  G06F1/26 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/329

Abstract: Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.

Abstract translation: 公开了调试有限状态机的方法和装置。 该方法包括实现调试逻辑电路并将调试逻辑电路连接到片上系统（SoC）电压源。 该方法包括操作将SoC从低功率状态序列到下一个低功率状态并产生对应于低功率状态的相应输出信号的有限状态机，并且其中有限状态机连接到始终开启电压源。 该方法包括屏蔽输出信号以产生相应的屏蔽输出信号，以及将屏蔽的输出信号施加到SoC电路元件以防止转换到低功率状态并因此使调试逻辑电路保持活动。 该方法包括通过调试逻辑电路调试处于最低功耗状态的有限状态机。

公开(公告)号：US20150212154A1

公开(公告)日：2015-07-30

申请号：US14165871

申请日：2014-01-28

Applicant: Nvidia Corporation

Inventor： Padam Krishnani ,  Supreet Agrawal ,  Kwanjee Ng

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31705 ,  G01R31/31721 ,  G06F1/26 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/329

Abstract: Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit.

Abstract translation: 公开了调试有限状态机的方法和装置。 该方法包括实现调试逻辑电路并将调试逻辑电路连接到片上系统（SoC）电压源。 该方法包括操作将SoC从低功率状态序列到下一个低功率状态并产生对应于低功率状态的相应输出信号的有限状态机，并且其中有限状态机连接到始终开启电压源。 该方法包括屏蔽输出信号以产生相应的屏蔽输出信号，以及将屏蔽的输出信号施加到SoC电路元件以防止转换到低功率状态并因此使调试逻辑电路保持活动。 该方法包括通过调试逻辑电路调试处于最低功耗状态的有限状态机。