公开(公告)号：US09971576B2

公开(公告)日：2018-05-15

申请号：US14085649

申请日：2013-11-20

Applicant: Nvidia Corporation

Inventor： Stephen Jones ,  Mark Hairgrove ,  Jaydeep Marathe ,  Vivek Kini ,  Bastiaan Aarts

IPC: G06F8/30 ,  G06F8/41 ,  G06F9/45 ,  G06F9/44

CPC classification number: G06F8/41 ,  G06F8/30

Abstract: A software development environment (SDE) and a method of compiling integrated source code. One embodiment of the SDE includes: (1) a parser configured to partition an integrated source code into a host code partition and a device code partition, the host code partition including a reference to a device variable, (2) a translator configured to: (2a) embed device machine code, compiled based on the device code partition, into a modified host code, (2b) define a pointer in the modified host code configured to be initialized, upon execution of the integrated source code, to a memory address allocated to the device variable, and (2c) replace the reference with a dereference to the pointer, and (3) a host compiler configured to employ a host library to compile the modified host code.

公开(公告)号：US20180018750A1

公开(公告)日：2018-01-18

申请号：US15709397

申请日：2017-09-19

Applicant: NVIDIA Corporation

Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC: G06T1/20 ,  G06F9/50 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US10546361B2

公开(公告)日：2020-01-28

申请号：US15709397

申请日：2017-09-19

Applicant: NVIDIA Corporation

Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC: G06F13/14 ,  G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US20190147561A1

公开(公告)日：2019-05-16

申请号：US16237010

申请日：2018-12-31

Applicant: Nvidia Corporation

Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC: G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US12112395B2

公开(公告)日：2024-10-08

申请号：US16919954

申请日：2020-07-02

Applicant: Nvidia Corporation

Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC: G06F13/14 ,  G06F9/50 ,  G06F12/109 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/5016 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US10762593B2

公开(公告)日：2020-09-01

申请号：US16237010

申请日：2018-12-31

Applicant: Nvidia Corporation

Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC: G06F13/14 ,  G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US09632834B2

公开(公告)日：2017-04-25

申请号：US13897291

申请日：2013-05-17

Applicant: NVIDIA CORPORATION

Inventor： Vivek Kini ,  Forrest Iandola ,  Timothy James Murray

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/5038 ,  G06F9/30 ,  G06F9/3851 ,  G06F9/4881 ,  G06F2209/5021

Abstract: One embodiment sets forth a method for assigning priorities to kernels launched by a software application and executed within a stream of work on a parallel processing subsystem. First, the software application assigns a desired priority to a stream using a call included in the API. The API receives this call and passes it to a driver. The driver maps the desired priority to an appropriate device priority associated with the parallel processing subsystem. Subsequently, if the software application launches a particular kernel within the stream, then the driver assigns the device priority associated with the stream to the kernel before adding the kernel to the stream for execution on the parallel processing subsystem. Advantageously, by assigning priorities to streams and, subsequently, strategically launching kernels within the prioritized streams, an application developer may fine-tune the software application to increase the overall processing efficiency of the software application.

公开(公告)号：US09575760B2

公开(公告)日：2017-02-21

申请号：US13897123

申请日：2013-05-17

Applicant: NVIDIA CORPORATION

Inventor： Vivek Kini ,  Christopher Lamb

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06T1/20

CPC classification number: G06F9/38 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/5038 ,  G06F2209/5021 ,  G06T1/20

Abstract: One embodiment sets forth a method for assigning priorities to kernels launched by a software application and executed within a stream of work on a parallel processing subsystem that supports dynamic parallelism. First, the software application assigns a maximum nesting depth for dynamic parallelism. The software application then assigns a stream priority to a stream. These assignments cause a driver to map the stream priority to a device priority and, subsequently, associate the device priority with the stream. As part of the mapping, the driver ensures that each device priority is at least the maximum nesting depth higher than the device priorities associated with any lower priority streams. Subsequently, the driver launches any kernel included in the stream with the device priority associated with the stream. Advantageously, by strategically assigning the maximum nesting depth and prioritizing streams, an application developer may increase the overall processing efficiency of the software application.

Abstract translation: 一个实施例提出了一种用于为由软件应用发起的内核分配优先级并在支持动态并行性的并行处理子系统的工作流内执行的方法。 首先，软件应用程序为动态并行分配最大嵌套深度。 然后，软件应用程序将流优先级分配给流。 这些分配使驱动程序将流优先级映射到设备优先级，然后将设备优先级与流关联。 作为映射的一部分，驱动程序确保每个设备的优先级至少高于与任何较低优先级流相关联的设备优先级的最大嵌套深度。 随后，驱动程序使用与流相关联的设备优先级启动流中包含的任何内核。 有利地，通过策略性地分配最大嵌套深度和优先化流，应用开发者可以增加软件应用的整体处理效率。

公开(公告)号：US20150143347A1

公开(公告)日：2015-05-21

申请号：US14085649

申请日：2013-11-20

Applicant: NVIDIA CORPORATION

Inventor： Stephen Jones ,  Mark Hairgrove ,  Jaydeep Marathe ,  Vivek Kini ,  Bastiaan Aarts

IPC: G06F9/45

CPC classification number: G06F8/41 ,  G06F8/30

Abstract: A software development environment (SDE) and a method of compiling integrated source code. One embodiment of the SDE includes: (1) a parser configured to partition an integrated source code into a host code partition and a device code partition, the host code partition including a reference to a device variable, (2) a translator configured to: (2a) embed device machine code, compiled based on the device code partition, into a modified host code, (2b) define a pointer in the modified host code configured to be initialized, upon execution of the integrated source code, to a memory address allocated to the device variable, and (2c) replace the reference with a dereference to the pointer, and (3) a host compiler configured to employ a host library to compile the modified host code.

Abstract translation: 软件开发环境（SDE）和编译集成源代码的方法。 SDE的一个实施例包括：（1）被配置为将集成源代码分割成主机代码分区和设备代码分区的解析器，所述主机代码分区包括对设备变量的引用，（2）翻译器，被配置为： （2a）将基于所述设备代码分区编译的设备机器码嵌入修改的主机代码中，（2b）在执行所述集成源代码时将修改后的主机代码中的指针定义为被初始化的内容地址 分配给设备变量，并且（2c）将引用替换为指针的取消引用，以及（3）配置为使用主机库来编译修改的主机代码的主机编译器。

公开(公告)号：US20200265543A9

公开(公告)日：2020-08-20

申请号：US16237010

申请日：2018-12-31

Applicant: Nvidia Corporation

Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC: G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.