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    SOFTWARE DEVELOPMENT ENVIRONMENT AND METHOD OF COMPILING INTEGRATED SOURCE CODE
    2.
    发明申请
    SOFTWARE DEVELOPMENT ENVIRONMENT AND METHOD OF COMPILING INTEGRATED SOURCE CODE 有权
    软件开发环境和编译集成源代码的方法

    公开(公告)号：US20150143347A1

    公开(公告)日：2015-05-21

    申请号：US14085649

    申请日：2013-11-20

    Applicant: NVIDIA CORPORATION

    Inventor： Stephen Jones ,  Mark Hairgrove ,  Jaydeep Marathe ,  Vivek Kini ,  Bastiaan Aarts

    IPC: G06F9/45

    CPC classification number: G06F8/41 ,  G06F8/30

    Abstract: A software development environment (SDE) and a method of compiling integrated source code. One embodiment of the SDE includes: (1) a parser configured to partition an integrated source code into a host code partition and a device code partition, the host code partition including a reference to a device variable, (2) a translator configured to: (2a) embed device machine code, compiled based on the device code partition, into a modified host code, (2b) define a pointer in the modified host code configured to be initialized, upon execution of the integrated source code, to a memory address allocated to the device variable, and (2c) replace the reference with a dereference to the pointer, and (3) a host compiler configured to employ a host library to compile the modified host code.

    Abstract translation: 软件开发环境（SDE）和编译集成源代码的方法。 SDE的一个实施例包括：（1）被配置为将集成源代码分割成主机代码分区和设备代码分区的解析器，所述主机代码分区包括对设备变量的引用，（2）翻译器，被配置为： （2a）将基于所述设备代码分区编译的设备机器码嵌入修改的主机代码中，（2b）在执行所述集成源代码时将修改后的主机代码中的指针定义为被初始化的内容地址 分配给设备变量，并且（2c）将引用替换为指针的取消引用，以及（3）配置为使用主机库来编译修改的主机代码的主机编译器。

    Unified memory systems and methods
    4.
    发明授权
    Unified memory systems and methods 有权

    公开(公告)号：US12112395B2

    公开(公告)日：2024-10-08

    申请号：US16919954

    申请日：2020-07-02

    Applicant: Nvidia Corporation

    Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

    IPC: G06F13/14 ,  G06F9/50 ,  G06F12/109 ,  G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06F9/5016 ,  G06F12/109 ,  G06T1/60

    Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

    PCIe traffic tracking hardware in a unified virtual memory system
    6.
    发明授权
    PCIe traffic tracking hardware in a unified virtual memory system 有权

    公开(公告)号：US11210253B2

    公开(公告)日：2021-12-28

    申请号：US16450830

    申请日：2019-06-24

    Applicant: NVIDIA CORPORATION

    Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  James Leroy Deming ,  Brian Fahs ,  Mark Hairgrove ,  John Mashey

    IPC: G06F13/40 ,  G06F12/123 ,  G06F12/0864 ,  G06F12/0806 ,  G06F12/0875

    Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

    Unified memory systems and methods
    7.
    发明授权
    Unified memory systems and methods 有权

    公开(公告)号：US10762593B2

    公开(公告)日：2020-09-01

    申请号：US16237010

    申请日：2018-12-31

    Applicant: Nvidia Corporation

    Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

    IPC: G06F13/14 ,  G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

    Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

    Microcontroller for memory management unit
    9.
    发明授权
    Microcontroller for memory management unit 有权

    公开(公告)号：US09792220B2

    公开(公告)日：2017-10-17

    申请号：US14011655

    申请日：2013-08-27

    Applicant: NVIDIA CORPORATION

    Inventor： Cameron Buschardt ,  Jerome F. Duluk, Jr. ,  John Mashey ,  Mark Hairgrove ,  James Leroy Deming ,  Brian Fahs

    IPC: G06F12/00 ,  G06F12/1009

    CPC classification number: G06F12/1009 ,  G06F2212/301

    Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

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