公开(公告)号：US20240232360A1

公开(公告)日：2024-07-11

申请号：US18151175

申请日：2023-01-06

申请人： NVIDIA Corporation

发明人： Lucien Dunning ,  Seth Schneider ,  Dwayne Swoboda ,  Marko Mitic ,  Adam Zabrocki

IPC分类号： G06F21/57 ,  A63F13/73

CPC分类号： G06F21/57 ,  A63F13/73

摘要： In examples, a VM may receive and aggregate a first attestation report corresponding to a
CPU and a second attestation report corresponding to a GPU. The aggregated data may be provided to an attestation service, which may verify the attestation reports indicate a TCB is to include the VM and GPU state data and is to isolate the GPU state data and the VM from an untrusted host OS. Based at least on the TCB being verified, the VM may perform one or more operations using the TCB. The TCB may include a trusted hypervisor to isolate the VM and GPU state data within the GPU(s) from the untrusted host OS. The trusted hypervisor may prevent the host OS from accessing device memory assigned to the VM based at least on controlling an IOMMU and/or second-level address translation (SLAT) used to access the data.

公开(公告)号：US11741015B2

公开(公告)日：2023-08-29

申请号：US17820870

申请日：2022-08-18

申请人： NVIDIA CORPORATION

发明人： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey

IPC分类号： G06F11/07 ,  G06F12/08 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F12/10 ,  G06F12/1009

CPC分类号： G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/109 ,  G06F12/1072 ,  G06F12/12 ,  G06F12/10 ,  G06F2212/1016

摘要： A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US12112395B2

公开(公告)日：2024-10-08

申请号：US16919954

申请日：2020-07-02

申请人： Nvidia Corporation

发明人： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC分类号： G06F13/14 ,  G06F9/50 ,  G06F12/109 ,  G06T1/20 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06F9/5016 ,  G06F12/109 ,  G06T1/60

摘要： The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US20230297406A1

公开(公告)日：2023-09-21

申请号：US18123222

申请日：2023-03-17

申请人： NVIDIA Corporation

发明人： Philip Rogers ,  Mark Overby ,  Vyas Venkataraman ,  Naveen Cherukuri ,  James Leroy Deming ,  Gobikrishna Dhanuskodi ,  Dwayne Swoboda ,  Lucien Dunning ,  Aruna Manjunatha ,  Aaron Jiricek ,  Mark Hairgrove ,  Mike Woodmansee

IPC分类号： G06F9/455

CPC分类号： G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45587

摘要： In examples, trusted execution environments (TEE) are provided for an instance of a parallel processing unit (PPU) as PPU TEEs. Different instances of a PPU correspond to different PPU TEEs, and provide accelerated confidential computing to a corresponding TEE. The processors of each PPU instance have separate and isolated paths through the memory system of the PPU which are assigned uniquely to an individual PPU instance. Data in device memory of the PPU may be isolated and access controlled amongst the PPU instances using one or more hardware firewalls. A GPU hypervisor assigns hardware resources to runtimes and performs access control and context switching for the runtimes. A PPU instance uses a cryptographic key to protect data for secure communication. Compute engines of the PPU instance are prevented from writing outside of a protected memory region. Access to a write protected region in PPU memory is blocked from other computing devices and/or device instances.

公开(公告)号：US10762593B2

公开(公告)日：2020-09-01

申请号：US16237010

申请日：2018-12-31

申请人： Nvidia Corporation

发明人： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC分类号： G06F13/14 ,  G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

摘要： The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US09798487B2

公开(公告)日：2017-10-24

申请号：US15243909

申请日：2016-08-22

申请人： NVIDIA Corporation

发明人： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  James Leroy Deming ,  Lucien Dunning ,  Brian Fahs ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey ,  James M. Van Dyke

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122

CPC分类号： G06F3/0647 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/1009 ,  G06F12/122 ,  G06F2212/652

摘要： One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

公开(公告)号：US20240286043A1

公开(公告)日：2024-08-29

申请号：US18174163

申请日：2023-02-24

申请人： NVIDIA Corporation

发明人： Lucien Dunning ,  Seth Schneider ,  Dwayne Swoboda ,  Marko Mitic ,  Daniel Rohrer

IPC分类号： A63F13/73 ,  A63F13/75 ,  H04L9/40

CPC分类号： A63F13/73 ,  A63F13/75 ,  H04L63/20

摘要： In examples, properties of an execution environment may be verified for a game session to comply with security policies based at least on analyzing attestation reports generated using one or more host devices. Content items may be associated with the game session to indicate the verification for presentation with a live stream video of the game session, in a pre-recorded video of the game session, and/or in another user interface associated with the game session. A record of the verification may be stored in a database, and the database may be queried to display the content item and/or to determine whether the verification occurred. The attestation reports may include an attestation report(s) generated using an input device(s) used to capture user inputs for the game session, such as an input device used to control the game session and/or provide a video capture of the player during the game session.

公开(公告)号：US20200265543A9

公开(公告)日：2020-08-20

申请号：US16237010

申请日：2018-12-31

申请人： Nvidia Corporation

发明人： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC分类号： G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

摘要： The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US10445243B2

公开(公告)日：2019-10-15

申请号：US14055356

申请日：2013-10-16

申请人： NVIDIA CORPORATION

发明人： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1072 ,  G06F11/07 ,  G06F12/12 ,  G06F12/08 ,  G06F12/10

摘要： A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US10303616B2

公开(公告)日：2019-05-28

申请号：US14055382

申请日：2013-10-16

申请人： NVIDIA Corporation

发明人： Jerome F. Duluk, Jr. ,  Chenghuan Jia ,  John Mashey ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1072 ,  G06F11/07 ,  G06F12/12 ,  G06F12/08 ,  G06F12/10

摘要： A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.