Shallow trench isolation (STI) structure for CMOS image sensor

    公开(公告)号:US11862509B2

    公开(公告)日:2024-01-02

    申请号:US17319368

    申请日:2021-05-13

    Abstract: A shallow trench isolation (STI) structure and method of fabrication includes forming a shallow trench isolation (STI) structure having a polygonal shaped cross-section in a semiconductor substrate of an image sensor includes a two-step etching process. The first step is a dry plasma etch that forms a portion of the trench to a first depth. The second step is a wet etch process that completes the trench etching to the desired depth and cures damage caused by the dry etch process. A CMOS image sensor includes a semiconductor substrate having a photodiode region and a pixel transistor region separated by a shallow trench isolation (STI) structure having a polygonal shaped cross-section.

    High K metal-insulator-metal (MIM) capacitor network for lag mitigation

    公开(公告)号:US12177589B2

    公开(公告)日:2024-12-24

    申请号:US18154770

    申请日:2023-01-13

    Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A plurality of capacitor-switch pairs is coupled between the reset transistor and a bias voltage source. Each of the plurality of capacitor-switch pairs includes a lateral overflow integration capacitor (LOFIC) and a switch transistor coupled to the LOFIC.

    MULTILAYER REFLECTIVE STACK FOR REDUCING CROSSTALK IN SPLIT PIXEL IMAGE SENSORS

    公开(公告)号:US20240186353A1

    公开(公告)日:2024-06-06

    申请号:US18076084

    申请日:2022-12-06

    Abstract: An image sensor comprising a semiconductor substrate, a plurality of photodiodes, a multilayer reflective stack, and a dielectric layer is disclosed. The plurality of photodiodes is disposed within the semiconductor substrate and includes a first photodiode and a second photodiode adjacent to the first photodiode. The multilayer reflective stack comprises a first material having a first refractive index and a second material having a second refractive index. The dielectric layer has a third refractive index and is disposed between the first photodiode and the multilayer reflective stack. The first material is disposed between the second material and the dielectric layer. The first refractive index is greater than the second refractive index and the third refractive index.

    HIGH K METAL-INSULATOR-METAL (MIM) CAPACITOR NETWORK FOR LAG MITIGATION

    公开(公告)号:US20240244350A1

    公开(公告)日:2024-07-18

    申请号:US18154770

    申请日:2023-01-13

    CPC classification number: H04N25/77

    Abstract: A pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A plurality of capacitor-switch pairs is coupled between the reset transistor and a bias voltage source. Each of the plurality of capacitor-switch pairs includes a lateral overflow integration capacitor (LOFIC) and a switch transistor coupled to the LOFIC.

    Image sensor with elevated floating diffusion

    公开(公告)号:US11869906B2

    公开(公告)日:2024-01-09

    申请号:US16946743

    申请日:2020-07-02

    CPC classification number: H01L27/1461 H01L27/14643 H01L27/14689

    Abstract: A pixel cell with an elevated floating diffusion region is formed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.). The floating diffusion region can be elevated by separating a doped floating diffusion region from the semiconductor substrate by disposing an intervening layer (e.g., undoped, lightly doped, etc.) on the semiconductor substrate and beneath the doped floating diffusion region. For instance, the elevated floating diffusion region can be formed by stacked material layers composed of a lightly or undoped base or intervening layer and a heavy doped (e.g., As doped) “elevated” layer. In some examples, the stacked material layers can be formed by first and second epitaxial growth layers.

    SiGe Photodiode for Crosstalk Reduction

    公开(公告)号:US20220399393A1

    公开(公告)日:2022-12-15

    申请号:US17343553

    申请日:2021-06-09

    Abstract: SiGe photodiode for crosstalk reduction. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes. The plurality of pixels are configured to receive an incoming light through an illuminated surface of the semiconductor material. Each pixel includes a first photodiode comprising a silicon (Si) material; and a second photodiode having the Si material and a silicon germanium (SiGe) material.

    IMAGE SENSOR WITH ELEVATED FLOATING DIFFUSION

    公开(公告)号:US20220005846A1

    公开(公告)日:2022-01-06

    申请号:US16946743

    申请日:2020-07-02

    Abstract: A pixel cell with an elevated floating diffusion region is formed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.). The floating diffusion region can be elevated by separating a doped floating diffusion region from the semiconductor substrate by disposing an intervening layer (e.g., undoped, lightly doped, etc.) on the semiconductor substrate and beneath the doped floating diffusion region. For instance, the elevated floating diffusion region can be formed by stacked material layers composed of a lightly or undoped base or intervening layer and a heavy doped (e.g., As doped) “elevated” layer. In some examples, the stacked material layers can be formed by first and second epitaxial growth layers.

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