Apparatus and method for handling universal serial bus control transfers
    3.
    发明授权
    Apparatus and method for handling universal serial bus control transfers 失效
    用于处理通用串行总线控制传输的装置和方法

    公开(公告)号:US06205501B1

    公开(公告)日:2001-03-20

    申请号:US09004002

    申请日:1998-01-07

    IPC分类号: G06F1300

    CPC分类号: G06F13/385 G06F13/426

    摘要: A method and apparatus for performing a control transfer on a Universal Serial Bus (USB) device. A USB device includes a memory space for reading and writing data transmitted over a USB network. The memory space is shared between a plurality of endpoints. A host initiates a control transfer by transmitting a SETUP token to a first endpoint. The endpoint must accept the SETUP token. If the first endpoint does not expect the SETUP token, or if another endpoint is active, the device stores the token until a buffer is allocated and the first endpoint is made active.

    摘要翻译: 一种用于在通用串行总线(USB)设备上执行控制传送的方法和装置。 USB设备包括用于读取和写入通过USB网络发送的数据的存储器空间。 存储器空间在多个端点之间共享。 主机通过将SETUP令牌发送到第一端点来发起控制传送。 端点必须接受SETUP令牌。 如果第一个端点不期望SETUP令牌,或者另一个端点处于活动状态,则设备将存储令牌,直到缓冲区被分配并使第一个端点处于活动状态。

    Apparatus and method for implementing a versatile USB endpoint pipe
    4.
    发明授权
    Apparatus and method for implementing a versatile USB endpoint pipe 失效
    用于实现通用USB端点管的装置和方法

    公开(公告)号:US6070208A

    公开(公告)日:2000-05-30

    申请号:US3963

    申请日:1998-01-07

    申请人: David Brief

    发明人: David Brief

    IPC分类号: G06F13/42 G06F9/445

    CPC分类号: G06F13/4295 G06F13/426

    摘要: An apparatus for and method of controlling a versatile USB endpoint pipe are disclosed. The USB endpoint pipe can be in various states which are determined by control commands. The control commands also determine the endpoint pipe type.

    摘要翻译: 公开了一种用于控制多功能USB端点管的装置和方法。 USB端点管可以处于由控制命令确定的各种状态。 控制命令还确定端点管道类型。

    Method and apparatus for advanced interprocess communication
    5.
    发明授权
    Method and apparatus for advanced interprocess communication 有权
    高级进程间通信的方法和装置

    公开(公告)号:US08286188B1

    公开(公告)日:2012-10-09

    申请号:US12110717

    申请日:2008-04-28

    申请人: David Brief

    发明人: David Brief

    IPC分类号: G06F13/00

    CPC分类号: G06F9/544 G06F13/1663

    摘要: An interprocess memory controller is described that may be used to provide multiple processes within a multi-process device with access to a shared physical memory. The described interprocess memory controller may enforce access rights to shared memory that has been allocated to the respective processes, thereby guarding the multi-process device from instability due to the unauthorized overwriting and/or unauthorized freeing of allocated memory. The described interprocess memory controller approach may streamline interprocess communication by allowing data associated with an interprocess communication to be passed from a first process to a second process by passing a pointer as well as access rights to a buffer in shared memory that contains the message data. In this manner, the described interprocess memory controller approach may avoid the inefficiency of interprocess communication approaches that copy message data from a shared memory controlled by a first process to a shared memory controlled by a second process.

    摘要翻译: 描述了可以用于在多进程设备内提供对共享物理存储器的访问的多个进程的进程间存储器控制器。 所描述的进程间存储器控制器可以强制已经分配给相应进程的共享存储器的访问权限,从而由于未经授权的重写和/或未经授权释放所分配的存储器来保护多进程设备不稳定。 所描述的进程间存储器控制器方法可以通过允许与进程间通信相关联的数据从第一进程传递到第二进程来简化进程间通信,方法是将指针以及访问权限传递到包含消息数据的共享存储器中的缓冲器。 以这种方式,所描述的进程间存储器控制器方法可以避免将由第一进程控制的共享存储器中的消息数据复制到由第二进程控制的共享存储器的进程间通信方法的低效率。

    Asymmetric Differential Timing
    6.
    发明申请
    Asymmetric Differential Timing 审中-公开
    不对称差分时序

    公开(公告)号:US20070104228A1

    公开(公告)日:2007-05-10

    申请号:US11555283

    申请日:2006-11-01

    IPC分类号: H04J3/06

    CPC分类号: H04J3/0691

    摘要: A system and method for reconstructing a service clock between two, first and second subsystems communicating therebetween, comprising a first subsystem operative to generate first subsystem timestamps, a second subsystem operative to generate second subsystem timestamps at a second frequency different from the first timestamps, wherein the generations of both first and second timestamps are based on sampling of the service clock by a common clock available at both subsystems, and an aligner for arithmetically aligning the different first and second subsystem timestamps to reconstruct the service clock.

    摘要翻译: 一种用于重建在其间通信的两个第一和第二子系统之间的服务时钟的系统和方法,包括:第一子系统,用于产生第一子系统时间戳;第二子系统,用于以不同于所述第一时间戳的第二频率生成第二子系统时间戳,其中 第一和第二时间戳的代都基于通过在两个子系统可用的公共时钟的服务时钟的采样,以及用于对不同的第一和第二子系统时间戳进行算术对准以重构服务时钟的对准器。

    Increasing the availability of the universal serial bus interconnects
    7.
    发明授权
    Increasing the availability of the universal serial bus interconnects 失效
    增加通用串行总线互连的可用性

    公开(公告)号:US5903777A

    公开(公告)日:1999-05-11

    申请号:US942774

    申请日:1997-10-02

    申请人: David Brief

    发明人: David Brief

    摘要: A Universal Serial Bus hub circuit includes an upstream port and a plurality of downstream ports. The hub circuit further includes input circuitry via which data received on one of the downstream ports is to be repeated to the upstream port. Asynchronous event detection circuitry is to detect an asynchronous event in the received data for the one downstream port. Port selection circuitry to select the one downstream port. Timer circuitry is to measure a time period from a time that the asynchronous event detection circuitry detects an asynchronous event. Synchronous event detection circuitry is to detect a synchronous event in the received data for the one port. End-of-event generation circuitry generates a simulated end-of-event signal if the detected synchronous event is not before the end of the measured time period, and provides the simulated end-of-event signal to the upstream port.

    摘要翻译: 通用串行总线集线器电路包括上游端口和多个下游端口。 集线器电路还包括输入电路,通过该输入电路将在一个下游端口上接收的数据重复到上游端口。 异步事件检测电路是检测一个下行端口的接收数据中的异步事件。 端口选择电路选择一个下行端口。 定时器电路是测量从异步事件检测电路检测到异步事件的时间段。 同步事件检测电路是检测一个端口的接收数据中的同步事件。 如果检测到的同步事件不在测量的时间段结束之前,事件结束事件生成电路产生模拟的事件结束信号,并将模拟的事件结束信号提供给上行端口。

    Apparatus and method of transmitting and receiving USB isochronous data
    8.
    发明授权
    Apparatus and method of transmitting and receiving USB isochronous data 有权
    发送和接收USB同步数据的装置和方法

    公开(公告)号:US06678760B2

    公开(公告)日:2004-01-13

    申请号:US10013996

    申请日:2001-12-11

    申请人: David Brief

    发明人: David Brief

    IPC分类号: G06F1314

    CPC分类号: G06F13/385

    摘要: An apparatus for and method of transmitting and synchronizing isochronous data on a USB endpoint pipe are disclosed. Also disclosed are a double buffering capability, a transmission delay capability, a synchronization capability, and a clock adjustment capability.

    摘要翻译: 公开了一种用于在USB端点管上传输和同步同步数据的装置和方法。 还公开了双缓冲能力,传输延迟能力,同步能力和时钟调整能力。

    Apparatus and method for providing an interface to a compound Universal
Serial Bus controller
    9.
    发明授权
    Apparatus and method for providing an interface to a compound Universal Serial Bus controller 失效
    用于向复合通用串行总线控制器提供接口的装置和方法

    公开(公告)号:US6157975A

    公开(公告)日:2000-12-05

    申请号:US4005

    申请日:1998-01-07

    IPC分类号: G06F13/38 G06F13/42 G06F9/445

    CPC分类号: G06F13/385 G06F13/4295

    摘要: A method and apparatus for providing a programming interface to a Universal Serial Bus Device. The programming interface is partitioned so that an external controller does not handle intermediate transfers such as packet retry, handshake packets or intermediate response to error conditions. The programming model consists of a number of endpoint pipes, each of which can be configured to provide one of several functions.

    摘要翻译: 一种用于向通用串行总线设备提供编程接口的方法和装置。 编程接口被分区,使外部控制器不处理诸如分组重试,握手分组或对错误状态的中间响应之类的中间传输。 编程模型由多个端点管道组成,每个终端管道可以配置为提供几个功能之一。