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    Asymmetric Differential Timing
    1.
    发明申请
    Asymmetric Differential Timing 审中-公开
    不对称差分时序

    公开(公告)号：US20070104228A1

    公开(公告)日：2007-05-10

    申请号：US11555283

    申请日：2006-11-01

    申请人： Ron Cohen ,  Bar Gal-On ,  Zohar Peleg ,  David Brief

    发明人： Ron Cohen ,  Bar Gal-On ,  Zohar Peleg ,  David Brief

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0691

    摘要： A system and method for reconstructing a service clock between two, first and second subsystems communicating therebetween, comprising a first subsystem operative to generate first subsystem timestamps, a second subsystem operative to generate second subsystem timestamps at a second frequency different from the first timestamps, wherein the generations of both first and second timestamps are based on sampling of the service clock by a common clock available at both subsystems, and an aligner for arithmetically aligning the different first and second subsystem timestamps to reconstruct the service clock.

    摘要翻译： 一种用于重建在其间通信的两个第一和第二子系统之间的服务时钟的系统和方法，包括：第一子系统，用于产生第一子系统时间戳;第二子系统，用于以不同于所述第一时间戳的第二频率生成第二子系统时间戳，其中 第一和第二时间戳的代都基于通过在两个子系统可用的公共时钟的服务时钟的采样，以及用于对不同的第一和第二子系统时间戳进行算术对准以重构服务时钟的对准器。

    Interface for a memory unit
    4.
    发明授权
    Interface for a memory unit 有权
    存储单元的接口

    公开(公告)号：US06507899B1

    公开(公告)日：2003-01-14

    申请号：US09460534

    申请日：1999-12-13

    申请人： Klaus Oberlaender ,  Sabeen Randhawa ,  Yannick Martelloni ,  Manfred Henftling ,  Rami Zemach ,  Zohar Peleg ,  Christian Wiedholz ,  Gigy Baror ,  Doron Shoham ,  Oded Trainin ,  Niv Margalit

    发明人： Klaus Oberlaender ,  Sabeen Randhawa ,  Yannick Martelloni ,  Manfred Henftling ,  Rami Zemach ,  Zohar Peleg ,  Christian Wiedholz ,  Gigy Baror ,  Doron Shoham ,  Oded Trainin ,  Niv Margalit

    IPC分类号： G06F1208

    CPC分类号： G06F12/0215

    摘要： An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.

    摘要翻译： 描述了一种用于将数据处理单元与具有控制输入，地址信号输入，数据信号输入和数据信号输出的存储单元耦合的接口电路。 接口电路包括具有输入和输出的地址缓冲器，所述输入接收来自所述数据处理单元的地址信号，第一多路复用器将所述存储单元与所述地址缓冲器的所述输出或所述地址信号相耦合，数据 具有输入和输出的缓冲器，所述输入接收来自所述数据处理单元的数据信号，并且所述输出与所述存储器数据输入耦合;第二多路复用器，用于选择所述存储器数据信号输出或所述数据缓冲器输出;以及比较器 用于将所述地址信号与来自所述地址缓冲器输出的信号进行比较，产生控制所述第二多路复用器的控制信号。

    High resolution, multi-frequency digital phase-locked loop
    5.
    发明授权
    High resolution, multi-frequency digital phase-locked loop 失效
    高分辨率，多频数字锁相环

    公开(公告)号：US5218314A

    公开(公告)日：1993-06-08

    申请号：US890691

    申请日：1992-05-29

    申请人： Avner Efendovich ,  Afek Yachin ,  Amos Intrater ,  Zohar Peleg ,  Coby Sella ,  Zeev Bikowsky

    发明人： Avner Efendovich ,  Afek Yachin ,  Amos Intrater ,  Zohar Peleg ,  Coby Sella ,  Zeev Bikowsky

    IPC分类号： H03L7/00

    CPC分类号： H03L7/00

    摘要： The present invention provides a phase-locked loop in which an internal oscillator is fed into a high resolution tapped delay line. One output of the tapped delay line is selected by selection logic to generate the output clock. The output clock is phase compared with the input signal, which is either a clock signal or a NRZ data signal, and in any case, is a signal with frequency that is a division by two of the frequency of the internal oscillator and the source of which is also the internal oscillator. Then a decision is made, according to the phase detection, whether to select the next output of the delay line, the previous one, or remain with the current one. Therefore, if a change in the frequency is needed, then if an integer multiple or division of the original frequency is selected for the internal oscillator, synchronization will be unchanged, and furthermore, both the output clock and the input signal will simultaneously switch to the new frequency. All this is done by additional logic that enables actual switching to the new frequency only after an entire cycle of the low frequency has ended.

    摘要翻译： 本发明提供一种锁相环，其中将内部振荡器馈入高分辨率抽头延迟线。 抽头延迟线的一个输出由选择逻辑选择以产生输出时钟。 输出时钟与输入信号进行相位比较，输入信号是时钟信号或NRZ数据信号，在任何情况下都是频率为内部振荡器的频率除以2的信号， 这也是内部振荡器。 然后，根据相位检测，决定是选择延迟线的下一个输出，前一个还是与当前延迟线保持一致。 因此，如果需要频率变化，则如果为内部振荡器选择原始频率的整数倍或除法，同步将不变，此外，输出时钟和输入信号都将同时切换到 新频率 所有这些都是通过额外的逻辑完成的，只有在低频的整个周期结束后才能实际切换到新频率。