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1.发明申请Integrated-circuit chip with offset external pads and method for fabricating such a chip 有权具有偏移外部焊盘的集成电路芯片和用于制造这种芯片的方法公开(公告)号：US20070228508A1
公开(公告)日：2007-10-04
申请号：US11726353
申请日：2007-03-19
IPC分类号： H01L29/00
CPC分类号： H01L24/13 , H01L21/76897 , H01L23/525 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05644 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01022 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： An integrated-circuit chip includes a first electrical connection are placed on an underlying layer and covered with an intermediate dielectric layer. A second electrical connection is placed on the intermediate dielectric layer and is covered with a superficial dielectric layer. External electrical connection pads are placed on the superficial dielectric layer and extend selectively over the first electrical connection. Vias pass through the superficial dielectric layer and the intermediate dielectric layer to make connection between the first electrical connection and the external electrical connection pads.
摘要翻译： 集成电路芯片包括第一电连接被放置在下层并且被中间介电层覆盖。 第二电连接被放置在中间电介质层上并被表面电介质层覆盖。 外部电连接焊盘放置在表面电介质层上并选择性地延伸到第一电连接上。 通孔穿过表面电介质层和中间介质层，以在第一电连接和外部电连接焊盘之间形成连接。
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2.发明授权Integrated-circuit chip with offset external pads and method for fabricating such a chip 有权具有偏移外部焊盘的集成电路芯片和用于制造这种芯片的方法公开(公告)号：US07701047B2
公开(公告)日：2010-04-20
申请号：US11726353
申请日：2007-03-19
CPC分类号： H01L24/13 , H01L21/76897 , H01L23/525 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05644 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01022 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： An integrated-circuit chip includes a first electrical connection are placed on an underlying layer and covered with an intermediate dielectric layer. A second electrical connection is placed on the intermediate dielectric layer and is covered with a superficial dielectric layer. External electrical connection pads are placed on the superficial dielectric layer and extend selectively over the first electrical connection. Vias pass through the superficial dielectric layer and the intermediate dielectric layer to make connection between the first electrical connection and the external electrical connection pads.
摘要翻译： 集成电路芯片包括第一电连接被放置在下层并且被中间介电层覆盖。 第二电连接被放置在中间电介质层上并被表面电介质层覆盖。 外部电连接焊盘放置在表面电介质层上并选择性地延伸到第一电连接上。 通孔穿过表面电介质层和中间介质层，以在第一电连接和外部电连接焊盘之间形成连接。
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3.发明申请Integrated circuit chip with external pads and process for fabricating such a chip 有权具有外部焊盘的集成电路芯片和用于制造这种芯片的工艺公开(公告)号：US20070132095A1
公开(公告)日：2007-06-14
申请号：US11607827
申请日：2006-11-30
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/12 , H01L2224/0401 , H01L2224/05093 , H01L2224/05644 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/00014
摘要： An integrated circuit chip has a dielectric surface layer and, below this layer, internal pads. The chip is fabricated by producing multiplicities of vias made of an electrically conducting material which pass through said surface layer and are positioned respectively above the internal pads. Projecting external contact pads are formed on the surface layer and connected respectively to the multiplicities of vias.
摘要翻译： 集成电路芯片具有电介质表面层，并且在该层下方具有内部焊盘。 该芯片通过产生通过所述表面层并分别位于内部焊盘上方的由导电材料制成的多个通孔来制造。 在表面层上形成投射外部接触焊盘，并分别连接到多个通孔。
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公开(公告)号：US07463252B2
公开(公告)日：2008-12-09
申请号：US10622417
申请日：2003-07-18
申请人： Céline Mas , Eric Benoit , Olivier Scouarnec , Olivier Le Briz
发明人： Céline Mas , Eric Benoit , Olivier Scouarnec , Olivier Le Briz
CPC分类号： G09G3/3208 , G09G5/346 , G09G2320/043 , G09G2320/046
摘要： A method and circuit for displaying an image by activation of pixels of an array screen based on an image stored in digital form in memory point rows of a frame memory, having a stand-by mode that provides, at a frequency proportional to the display frequency, a cyclic succession of offset values; and for each row address of the frame memory, activating pixels of a screen line associated with said address offset by a same offset value based on the read states of the row associated with the address, and/or activating pixels of a screen line associated with the row address based on the read states of the frame memory row associated with the address offset by a same offset value.
摘要翻译： 一种用于通过基于以数字形式存储的图像通过激活阵列屏幕的像素来显示图像的方法和电路，该帧存储器的存储器点行具有备用模式，其以与显示频率成比例的频率 ，偏移值的循环连续; 并且对于帧存储器的每个行地址，基于与地址相关联的行的读取状态来激活与所述地址偏移相关联的屏幕线的像素相同的偏移值，和/或激活与该地址相关联的屏幕线的像素 基于与地址偏移相关联的帧存储器行的读取状态相同的偏移值的行地址。
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公开(公告)号：US06952242B2
公开(公告)日：2005-10-04
申请号：US09881892
申请日：2001-06-15
CPC分类号： H04N3/2335 , H04N9/28
摘要： A control signal for controlling a correction circuit for at least one electron beam that scans a screen line by line, the amplitude of which varies along each line according to a curve of a first type determined by line parameters, each of the line parameters varying, from one line to another, according to a curve of the first type determined by column parameters.
摘要翻译： 一种用于控制至少一根电子束的校正电路的控制信号，其逐行扫描屏幕，其幅度根据由线路参数确定的第一类型的曲线沿着每一行变化，每个线路参数变化， 从一行到另一行，根据由列参数确定的第一种类型的曲线。
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6.发明授权公开(公告)号：US07755580B2
公开(公告)日：2010-07-13
申请号：US10917846
申请日：2004-08-13
申请人： Céline Mas , Eric Benoit , Olivier Scouarnec , Olivier Le Briz , Danika Chaussy , Philippe Maige
发明人： Céline Mas , Eric Benoit , Olivier Scouarnec , Olivier Le Briz , Danika Chaussy , Philippe Maige
CPC分类号： G09G3/3216 , G09G3/32 , G09G3/3283 , G09G2320/029 , G09G2320/043 , G09G2330/02 , G09G2330/021 , G09G2330/08 , G09G2330/12
摘要： A method for regulating the biasing voltage of column control circuits of an array screen formed of LEDs distributed in lines and columns, the column control circuits being adapted to turning on at least one LED of a line. The method includes increasing the biasing voltage when the current flowing through at least one activated LED is smaller than a determined luminance current and of decreasing the biasing voltage when the current flowing through each activated LED is equal to the determined luminance current.
摘要翻译： 一种用于调节由分布在列和列中的LED形成的阵列屏的列控制电路的偏置电压的方法，所述列控制电路适于接通线路的至少一个LED。 该方法包括当流过至少一个激活的LED的电流小于确定的亮度电流时增加偏置电压，并且当流过每个激活的LED的电流等于所确定的亮度电流时降低偏置电压。
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7.发明授权Display of an image on an array screen by selective addressing of screen lines 有权通过选择性地寻址屏幕线，在阵列屏幕上显示图像公开(公告)号：US07173640B2
公开(公告)日：2007-02-06
申请号：US10622368
申请日：2003-07-18
申请人： Céline Mas , Eric Benoit , Olivier Scouarnec , Olivier Le Briz
发明人： Céline Mas , Eric Benoit , Olivier Scouarnec , Olivier Le Briz
CPC分类号： G09G3/3208 , G09G5/39 , G09G2310/0251 , G09G2310/04 , G09G2330/021
摘要： A method for displaying an image on an array screen by activation of screen pixels arranged in rows and columns, each pixel of a same row corresponding to a memory point of a same memory row, the memory point being set to an activation state when the corresponding pixel is to be activated, including the steps of identifying, among sets of the memory rows, the row sets for which at least one memory point of a row of the set is at the activation state; and successively selecting the only lines corresponding to the rows of the sets of rows identified for the pixel activation. The present invention also provides a device for displaying an image on an array screen.
摘要翻译： 一种用于通过激活排列成行和列的屏幕像素而在阵列屏幕上显示图像的方法，每行与同一存储行的存储点对应的同一行的每个像素，当相应的存储点被设置为激活状态时 包括以下步骤：在所述存储器行的集合中识别所述集合的行的至少一个存储点处于所述激活状态的行集; 并且连续地选择与为像素激活识别的行集合对应的行。 本发明还提供了一种用于在阵列屏幕上显示图像的装置。
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8.发明授权Integrated circuit chip with external pads and process for fabricating such a chip 有权具有外部焊盘的集成电路芯片和用于制造这种芯片的工艺公开(公告)号：US07501704B2
公开(公告)日：2009-03-10
申请号：US11607827
申请日：2006-11-30
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/12 , H01L2224/0401 , H01L2224/05093 , H01L2224/05644 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2924/01013 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/00014
摘要： An integrated circuit chip has a dielectric surface layer and, below this layer, internal pads. The chip is fabricated by producing multiplicities of vias made of an electrically conducting material which pass through said surface layer and are positioned respectively above the internal pads. Projecting external contact pads are formed on the surface layer and connected respectively to the multiplicities of vias.
摘要翻译： 集成电路芯片具有电介质表面层，并且在该层下方具有内部焊盘。 该芯片通过产生通过所述表面层并分别位于内部焊盘上方的由导电材料制成的多个通孔来制造。 在表面层上形成投射外部接触焊盘，并分别连接到多个通孔。
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9.发明申请公开(公告)号：US20050035933A1
公开(公告)日：2005-02-17
申请号：US10917846
申请日：2004-08-13
申请人： Celine Mas , Eric Benoit , Olivier Scouarnec , Olivier Le Briz , Danika Chaussy , Philippe Maige
发明人： Celine Mas , Eric Benoit , Olivier Scouarnec , Olivier Le Briz , Danika Chaussy , Philippe Maige
CPC分类号： G09G3/3216 , G09G3/32 , G09G3/3283 , G09G2320/029 , G09G2320/043 , G09G2330/02 , G09G2330/021 , G09G2330/08 , G09G2330/12
摘要： A method for regulating the biasing voltage of column control circuits of an array screen formed of LEDs distributed in lines and columns, the column control circuits being adapted to turning on at least one LED of a line. The method consists of increasing the biasing voltage when the current flowing through at least one activated LED is smaller than a determined luminance current and of decreasing the biasing voltage when the current flowing through each activated LED is equal to the determined luminance current.
摘要翻译： 一种用于调节由分布在列和列中的LED形成的阵列屏的列控制电路的偏置电压的方法，所述列控制电路适于接通线路的至少一个LED。 该方法包括当流过至少一个激活的LED的电流小于确定的亮度电流时增加偏置电压，并且当流过每个激活的LED的电流等于所确定的亮度电流时降低偏置电压。
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