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    Upgradeable and reconfigurable programmable logic device
    1.
    发明申请
    Upgradeable and reconfigurable programmable logic device 有权
    可升级和可重新配置的可编程逻辑器件

    公开(公告)号：US20060232295A1

    公开(公告)日：2006-10-19

    申请号：US11455315

    申请日：2006-06-16

    申请人： Om Agrawal ,  Howard Tang ,  Jack Wong

    发明人： Om Agrawal ,  Howard Tang ,  Jack Wong

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17772 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768

    摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.

    摘要翻译： 公开了用于编程和/或重新配置这些设备的可编程逻辑器件和技术。 例如，根据本发明的实施例，公开了一种可编程逻辑器件，其包括闪速存储器和SRAM，并且包括用于对闪速存储器和/或SRAM进行编程的多个数据端口。

    Upgradeable and reconfigurable programmable logic device
    2.
    发明申请
    Upgradeable and reconfigurable programmable logic device 有权
    可升级和可重新配置的可编程逻辑器件

    公开(公告)号：US20050189962A1

    公开(公告)日：2005-09-01

    申请号：US10783886

    申请日：2004-02-20

    申请人： Om Agrawal ,  Howard Tang ,  Jack Wong

    发明人： Om Agrawal ,  Howard Tang ,  Jack Wong

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17772 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768

    摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.

    摘要翻译： 公开了用于编程和/或重新配置这些设备的可编程逻辑器件和技术。 例如，根据本发明的实施例，公开了一种可编程逻辑器件，其包括闪速存储器和SRAM，并且包括用于对闪速存储器和/或SRAM进行编程的多个数据端口。

    Upgradeable and reconfigurable programmable logic device
    3.
    发明授权
    Upgradeable and reconfigurable programmable logic device 有权
    可升级和可重新配置的可编程逻辑器件

    公开(公告)号：US07215139B2

    公开(公告)日：2007-05-08

    申请号：US11455315

    申请日：2006-06-16

    申请人： Om P. Agrawal ,  Howard Tang ,  Jack Wong

    发明人： Om P. Agrawal ,  Howard Tang ,  Jack Wong

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17772 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768

    摘要： Programmable logic devices and techniques for programming and/or reconfiguring these devices are disclosed. For example, in accordance with an embodiment of the present invention, a programmable logic device is disclosed that incorporates flash memory and SRAM and includes multiple data ports for programming the flash memory and/or the SRAM.

    摘要翻译： 公开了用于编程和/或重新配置这些设备的可编程逻辑器件和技术。 例如，根据本发明的实施例，公开了一种可编程逻辑器件，其包括闪速存储器和SRAM，并且包括用于对闪速存储器和/或SRAM进行编程的多个数据端口。

    METHOD AND SYSTEM FOR RADIO CONFIGURATION
    5.
    发明申请
    METHOD AND SYSTEM FOR RADIO CONFIGURATION 审中-公开
    无线电配置的方法和系统

    公开(公告)号：US20080045169A1

    公开(公告)日：2008-02-21

    申请号：US11460418

    申请日：2006-07-27

    申请人： Daniel P. Zetzl ,  Jack Wong

    发明人： Daniel P. Zetzl ,  Jack Wong

    IPC分类号： H04B1/18

    CPC分类号： H04B1/3822

    摘要： A system (100) and method (400) for radio configuring is provided. The method can include connecting (402) a non-volatile memory storage device (120) to a first radio (110) having a first radio configuration (112), saving (404) a list of radio configurable parameters (300) in the first radio to the non-volatile memory storage device, removing (406) the non-volatile memory storage device from the first radio, connecting (408) the non-volatile memory storage device to a second radio (130) having a second configuration (134), and copying (410) the list of radio configurable parameters from the non-volatile memory storage device to the second radio for replicating the first configuration on the second radio. The non-volatile memory storage device can be a Universal Serial Bus (USB) memory device, a portable Flash memory device, or a compact Flash device.

    摘要翻译： 提供了一种用于无线电配置的系统（100）和方法（400）。 该方法可以包括将非易失性存储器存储设备（120）连接到具有第一无线电配置（112）的第一无线电（110）（112），从而节省（404）第一无线电配置参数（300）的列表 将所述非易失性存储器存储设备无线电连接到所述非易失性存储器存储设备，从所述第一无线电中移除（406）所述非易失性存储器存储设备，将所述非易失性存储器存储设备连接（408）到具有第二配置的第二无线电（130） ），并且将所述无线电配置参数的列表（410）从所述非易失性存储器存储设备复制到所述第二无线电装置，以在所述第二无线电装置上复制所述第一配置。 非易失性存储器存储设备可以是通用串行总线（USB）存储设备，便携式闪存设备或小型闪存设备。

    Method and system for audio routing in a vehicle mounted communication system
    7.
    发明授权
    Method and system for audio routing in a vehicle mounted communication system 有权
    车载通信系统中音频路由的方法和系统

    公开(公告)号：US08509693B2

    公开(公告)日：2013-08-13

    申请号：US12784924

    申请日：2010-05-21

    申请人： Ellis A. Pinder ,  Jack Wong

    发明人： Ellis A. Pinder ,  Jack Wong

    IPC分类号： H04B7/00

    CPC分类号： H04M1/6091 ,  H04L65/4061 ,  H04W76/45

    摘要： A system and method for routing audio for a vehicle mounted communication system includes activating (210) a (Push-To-Talk) PTT button associated with a handheld or rear microphone and determining (220) whether a short range wireless device is operationally coupled with the vehicle mounted communication device. In accordance with an embodiment, first audio signals received (260) from a microphone of the short range wireless device are transmitted to a remote party (265) when the short range wireless device is operationally coupled to the vehicle mounted communication device. Second audio signals received (270) from a remote party are routed (275) to a speaker of the short range wireless device, when the short range wireless device is operationally coupled with the vehicle mounted communication device and the PTT button is activated.

    摘要翻译： 用于路由车载通信系统的音频的系统和方法包括激活（210）与手持或后置麦克风相关联的（一键通）PTT按钮，并且确定（220）短距离无线设备是否可操作地与 车载通信装置。 根据实施例，当短距离无线设备可操作地耦合到车载通信设备时，从短距离无线设备的麦克风接收的第一音频信号（260）被发送到远程方（265）。 当短距离无线设备与车载通信设备可操作地耦合并且PTT按钮被激活时，从远程方接收的第二音频信号（270）被路由（275）到短距离无线设备的扬声器。

    Direct access arrangement device
    8.
    发明授权
    Direct access arrangement device 有权
    直接访问安排设备

    公开(公告)号：US07835516B2

    公开(公告)日：2010-11-16

    申请号：US11321262

    申请日：2005-12-29

    申请人： Jack Wong

    发明人： Jack Wong

    IPC分类号： H04M7/04

    CPC分类号： H04M11/066 ,  H04M11/04

    摘要： A direct access arrangement (DAA) device configured to interface a security alarm modem with a phone network. The DAA device comprises a receive optical isolator (OI) module and first and second transmit OI modules. The transmit OI modules are joined in parallel with one another to receive signals from the security alarm modem and convey the signals to the phone network. The receive IO and first and second transmit OI modules may each be interconnected to at least partially cancel distortion generated by the first and second transmit IO modules.

    摘要翻译： 一种直接接入装置（DAA）装置，被配置为将安全警报调制解调器与电话网络接口。 DAA设备包括接收光隔离器（OI）模块和第一和第二传输OI模块。 传输OI模块彼此并联连接，以从安全警报调制解调器接收信号，并将信号传送到电话网络。 接收IO和第一和第二传输OI模块可以各自互连以至少部分地消除由第一和第二传输IO模块产生的失真。

    Intelligent watchdog circuit
    9.
    发明申请
    Intelligent watchdog circuit 失效
    智能看门狗电路

    公开(公告)号：US20070101205A1

    公开(公告)日：2007-05-03

    申请号：US11193677

    申请日：2005-10-28

    申请人： Challis Purrington ,  Christopher West ,  Jack Wong ,  Maya Yarbrough

    发明人： Challis Purrington ,  Christopher West ,  Jack Wong ,  Maya Yarbrough

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0757

    摘要： A simple, but intelligent watchdog circuit uses an up/down counter for its delay element. A watchdog event will occur if the counter is allowed to over flow or under flow its boundaries (in either direction). The system objective is to keep the counter within its boundaries by controlling the direction of the count. The count direction is simply a function of the Most Significant Bit (MSB) of the counter. Thus, the system must simply monitor the counters MSB and perform a little intelligent to determine the desired count direction.

    摘要翻译： 一个简单但智能的看门狗电路使用一个向上/向下计数器作为其延迟元件。 如果计数器允许超过流量或流过其边界（在任一方向），将会发生看门狗事件。 系统目标是通过控制计数方向来保持柜台在其边界内。 计数方向只是计数器的最高有效位（MSB）的函数。 因此，系统必须简单地监视计数器MSB并执行一点智能来确定所需的计数方向。

    Field programmable gate array having embedded memory with configurable depth and width
    10.
    发明授权
    Field programmable gate array having embedded memory with configurable depth and width 有权
    具有可配置深度和宽度的嵌入式存储器的现场可编程门阵列

    公开(公告)号：US06919736B1

    公开(公告)日：2005-07-19

    申请号：US10620286

    申请日：2003-07-14

    申请人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Bai Nguyen ,  Yu Huang ,  Jack Wong

    发明人： Om P. Agrawal ,  Bradley A. Sharpe-Geisler ,  Bai Nguyen ,  Yu Huang ,  Jack Wong

    IPC分类号： G06F17/50 ,  H03K19/177

    CPC分类号： H03K19/17796 ,  G06F17/5054

    摘要： A field programmable gate array (FPGA) has plural columns of run-time memory provided in each of one or more partitions. Each column of run-time memory has a plurality of configurable memory blocks (CMB's). Each CMB is programmably configurable at least into a shallow-and-widest mode where data words have a maximum bit width and into a deep-and-narrowest mode where data words have a minimum bit width. Each CMB spans plural interconnect buses and the bits of its widest data words are distributed among the spanned interconnect buses. When a deep-and-narrow mode is invoked, CMB's of alternate columns operate in complementary fashion so that bits of narrowed words from one CMB move through a first subset of the interconnect buses while bits of narrowed words from a second CMB, in an alternate column, move through a second subset of the interconnect buses, where the second subset is mutually exclusive of the first subset of the interconnect buses. On the other hand, when the shallow-and-widest mode is invoked, the bits of the wide words of CMB's in alternate columns shared interconnect buses on an overlapping basis. In one embodiment, the shared interconnect buses are tri-statable. Programmable joiners are provided for joining or disjoining the tri-statable interconnect buses of adjacent partitions.

    摘要翻译： 现场可编程门阵列（FPGA）具有在一个或多个分区中的每一个中提供的多列运行时存储器。 每列运行时存储器具有多个可配置存储器块（CMB）。 每个CMB可编程地至少配置为浅和最宽的模式，其中数据字具有最大位宽度，并且成为数据字具有最小位宽度的最深和最窄模式。 每个CMB跨越多个互连总线，其最宽的数据字的位分布在跨接互连总线之间。 当调用深而窄的模式时，CMB的备用列以互补方式运行，使得来自一个CMB的窄字的位移动通过互连总线的第一子集，同时来自第二CMB的窄字的位置 列移动穿过互连总线的第二子集，其中第二子集与互连总线的第一子集相互排斥。 另一方面，当调用浅和最宽模式时，CMB在备用列中的宽字的位以重叠的基础共享互连总线。 在一个实施例中，共享互连总线是三态的。 可编程连接器用于连接或分离相邻分区的三态互连总线。