公开(公告)号：US6028446A

公开(公告)日：2000-02-22

申请号：US118200

申请日：1998-07-17

申请人： Om P. Agrawal ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Kerry A. Ilgenstein

IPC分类号： H03K19/177 ,  H03K7/38

CPC分类号： H03K19/17736 ,  H03K19/17728 ,  H03K19/1774

摘要： A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the appropriate product term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.

摘要翻译： 可编程逻辑器件（PLD）单元用于构建高密度高性能可编程逻辑器件（PLD）。 PLD单元包括两个可编程逻辑块单元。 PLD单元还包括I / O单元和输入宏单元。 此外，PLD单元包括可编程输出开关矩阵组的子组和可编程输入开关矩阵组的子组。 每个可编程逻辑块单元包括多个乘积项。 集群中至少有一个产品术语可编程地可用于集群。 当产品术语与集群断开连接时，产品术语用于控制逻辑宏单元输出信号或异步功能的极性。 因此，可编程可连接产品术语可用于同步或异步操作。 如果可编程可连接和可断开的产品术语连接到产品术语集群，则可编程逻辑块单元用于同步操作。 然而，由于每个产品项集合与逻辑宏单元相关联，所以逻辑宏单元可以通过简单地从产品项集群中断开适当的产品项并使用所需的异步功能的乘积项来单独配置用于异步操作。 因此，使用可编程逻辑块单元构建的单个PLD同时支持同步和异步操作。

公开(公告)号：US4963768A

公开(公告)日：1990-10-16

申请号：US243574

申请日：1988-09-12

申请人： Om P. Agrawal ,  Kerry A. Ilgenstein ,  Michael J. Wright ,  Jerry D. Moench ,  Arthur H. Khu

发明人： Om P. Agrawal ,  Kerry A. Ilgenstein ,  Michael J. Wright ,  Jerry D. Moench ,  Arthur H. Khu

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17708 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/17744

摘要： A high density segmented programmable array logic device utilizes a switch interconnection matrix to couple an array of programmable logic cells. Each programmable logic cell includes programmable input logic macrocells, programmable feedback logic macrocells, programmable output logic macrocells, buried state logic macrocells and an assembly of programmable AND gates and OR gates. Each input macrocell, output macrocell and buried state macrocell has means for generating either a registered/latched output signal or a combinatorial output signal in response to an input signal to the cell. The various switches are used to couple signals to or from the assembly of programmable AND gates and OR gates.

摘要翻译： 高密度分段可编程阵列逻辑器件利用开关互连矩阵耦合可编程逻辑单元阵列。 每个可编程逻辑单元包括可编程输入逻辑宏单元，可编程反馈逻辑宏单元，可编程输出逻辑宏单元，埋入状态逻辑宏单元以及可编程与门和或门组合。 每个输入宏单元，输出宏单元和掩埋状态宏单元具有用于响应于对单元的输入信号而产生已注册/锁存的输出信号或组合输出信号的装置。 各种开关用于将信号耦合到可编程“与”门和“或”门的组合。

公开(公告)号：US06348813B1

公开(公告)日：2002-02-19

申请号：US09721153

申请日：2000-11-22

申请人： Om P. Agrawal ,  Claudia A. Stanley ,  Xiaojie (Warren) He ,  Larry R. Metzger ,  Robert A. Simon ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Claudia A. Stanley ,  Xiaojie (Warren) He ,  Larry R. Metzger ,  Robert A. Simon ,  Kerry A. Ilgenstein

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1778

摘要： An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.

摘要翻译： 改进的，可扩展的CPLD设备具有由全局交换矩阵（GSM）和偶数段分段交换矩阵（SSM）组成的双层分层交换结构。 偶数个超级逻辑块（SLB）耦合到每个SSM。 每个SSM及其SLB定义了一个与GSM相连的段。 每个SLB具有相对较多的输入（至少80），并且可以生成作为从SSM向SLB输入提供的独立输入项的乘积的产品项信号（PT）。 每个SLB中生成的某些产品术语专用于SLB本地控件。 每个SLB具有至少32个宏单元和至少16个I / O焊盘，其向本地SSM和全球GSM反馈。 在每个段内确保100％的段内连接性，以便每个段可用作独立的小型CPLD。 每个SSM都有额外的线路，专用于分段（全球）通信。 每个SLB的大量并行输入轻松实现64位宽的设计。 每个片段设计中的对称性允许更精细的粒化实现，例如32或16位宽的设计。

公开(公告)号：US5457409A

公开(公告)日：1995-10-10

申请号：US924685

申请日：1992-08-03

申请人： Om P. Agrawal ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17796 ,  H03K19/17704 ,  H03K19/17792

摘要： The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells.

摘要翻译： 本发明的可编程逻辑器件（PLD）包括通过包括可编程输入开关矩阵（输入开关矩阵）和可编程集中式开关矩阵（集中式开关矩阵））的可编程开关矩阵互连的两个或多个可编程逻辑块。 每个可编程逻辑块仅从集中式交换矩阵接收输入信号。 来自可编程逻辑块的输出信号通过输出开关矩阵耦合到多个输入/输出（I / O）引脚。 来自可编程逻辑块的输出信号也直接馈送到可编程输入开关矩阵。 此外，输入宏单元将驱动输入宏单元的I / O引脚上的信号（即，相关联的I / O引脚）耦合到可编程输入开关矩阵。 每个可编程逻辑块包括可编程逻辑阵列，可编程逻辑分配器和可编程逻辑宏单元。

公开(公告)号：US6150841A

公开(公告)日：2000-11-21

申请号：US326140

申请日：1999-06-06

申请人： Om P. Agrawal ,  Claudia A. Stanley ,  Xiaojie (Warren) He ,  Chong M. Lee ,  Robert M. Balzli, Jr. ,  Larry R. Metzger ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Claudia A. Stanley ,  Xiaojie (Warren) He ,  Chong M. Lee ,  Robert M. Balzli, Jr. ,  Larry R. Metzger ,  Kerry A. Ilgenstein

IPC分类号： H03K19/177

CPC分类号： H03K19/17728

摘要： An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.

摘要翻译： 改进的CPLD包括多个宏单元模块（MM），其中每个MM可以接收相对大量的独立输入（至少80个），并且可以从其产生至少5个不同的产品项信号（PT）。 所有5个PT可用于生成本地产品总和（SoP）。 5个PT中的任何一个可能被窃取（转向），而是为其宏小区模块提供本地控制。 每个模块包括一个本地产生SoS的门，它可以产生一个总和信号（SoS），它们表示相邻宏单元模块的SoP信号中的一个或多个本地SoP信号的布尔和，以及SoS信号的SoS信号 相邻的宏单元模块。 可以使用简单的分配和超分配来产生相对较大的一遍函数深度的和和信号，例如一次通过中的160PT。

公开(公告)号：US5869981A

公开(公告)日：1999-02-09

申请号：US479872

申请日：1995-06-06

申请人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。 第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。

公开(公告)号：US5489857A

公开(公告)日：1996-02-06

申请号：US924201

申请日：1992-08-03

申请人： Om P. Agrawal ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1774 ,  H03K19/17704 ,  H03K19/17716

摘要： A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the apropriate produce term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.

摘要翻译： 可编程逻辑器件（PLD）单元用于构建高密度高性能可编程逻辑器件（PLD）。 PLD单元包括两个可编程逻辑块单元。 PLD单元还包括I / O单元和输入宏单元。 此外，PLD单元包括可编程输出开关矩阵组的子组和可编程输入开关矩阵组的子组。 每个可编程逻辑块单元包括多个乘积项。 集群中至少有一个产品术语可编程地可用于集群。 当产品术语与集群断开连接时，产品术语用于控制逻辑宏单元输出信号或异步功能的极性。 因此，可编程可连接产品术语可用于同步或异步操作。 如果可编程可连接和可断开的产品术语连接到产品术语集群，则可编程逻辑块单元用于同步操作。 然而，由于每个产品项集合与逻辑宏单元相关联，所以逻辑宏单元可以通过简单地从产品项集群中断开适当的产出项并且使用产品项用于期望的异步功能来单独配置用于异步操作。 因此，使用可编程逻辑块单元构建的单个PLD同时支持同步和异步操作。

公开(公告)号：US5225719A

公开(公告)日：1993-07-06

申请号：US699427

申请日：1991-05-13

申请人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  George H. Landers ,  Nicholas A. Schmitz ,  Jerry D. Moench ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17708 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

摘要： Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell. In a first PLD of each family, a first predetermined number of input lines couple the switch matrix to each programmable logic block. In a second PLD of each family, a second predetermined number of input lines couple the switch matrix to each programmable logic block. The number of input lines to each programmable logic block and to the switch matrix are selected to provide a predetermined routability factor. The second family of PLDs has a larger pin to logic ratio than the first family of PLDs.

摘要翻译： 至少两个系列的高密度分段可编程阵列逻辑器件中的每个可编程逻辑器件利用可编程开关互连矩阵来耦合对称可编程逻辑块阵列。 每个可编程逻辑块包括可编程逻辑宏单元，可编程输入/输出宏单元，逻辑分配器和可编程产品项阵列。 可编程开关矩阵提供具有固定路径独立延迟的集中式全局路由，并将逻辑宏单元与产品项阵列分离。 逻辑分配器将产品项阵列与逻辑宏单元分离，并且I / O宏单元将逻辑宏单元与封装I / O引脚分离。 逻辑分配器将产品术语从产品术语数组转向选定的逻辑宏单元，使得不将产品术语永久分配给特定的逻辑宏单元。 在每个系列的第一PLD中，第一预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 在每个系列的第二PLD中，第二预定数量的输入线将开关矩阵耦合到每个可编程逻辑块。 选择到每个可编程逻辑块和开关矩阵的输入线的数量以提供预定的可布线因子。 第二系列PLD具有比第一个PLD系列更大的引脚与逻辑比。

公开(公告)号：US06184713B2

公开(公告)日：2001-02-06

申请号：US09326940

申请日：1999-06-06

申请人： Om P. Agrawal ,  Claudia A. Stanley ,  Xiaojie (Warren) He ,  Larry R. Metzger ,  Robert A. Simon ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Claudia A. Stanley ,  Xiaojie (Warren) He ,  Larry R. Metzger ,  Robert A. Simon ,  Kerry A. Ilgenstein

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/1778

摘要： An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications. The large number of parallel inputs to each SLB ease implementation of 64-bit wide designs. Symmetry within the design of each segment allow for more finely-granulated implementations such as for 32 or 16-bit wide designs.

摘要翻译： 改进的，可扩展的CPLD设备具有由全局交换矩阵（GSM）和偶数段分段交换矩阵（SSM）组成的双层分层交换结构。 偶数个超级逻辑块（SLB）耦合到每个SSM。 每个SSM及其SLB定义了一个与GSM相连的段。 每个SLB具有相对较多的输入（至少80），并且可以生成作为从SSM向SLB输入提供的独立输入项的乘积的产品项信号（PT）。 每个SLB中生成的某些产品术语专用于SLB本地控件。 每个SLB具有至少32个宏单元和至少16个I / O焊盘，其向本地SSM和全球GSM反馈。 在每个段内确保100％的段内连接性，以便每个段可用作独立的小型CPLD。 每个SSM都有额外的线路，专用于分段（全球）通信。 每个SLB的大量并行输入轻松实现64位宽的设计。 每个片段设计中的对称性允许更精细的粒化实现，例如32或16位宽的设计。

公开(公告)号：US5811986A

公开(公告)日：1998-09-22

申请号：US474635

申请日：1995-06-06

申请人： Om P. Agrawal ,  Kerry A. Ilgenstein

发明人： Om P. Agrawal ,  Kerry A. Ilgenstein

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K7/38

CPC分类号： H03K19/1774 ,  H03K19/17704 ,  H03K19/17716

摘要： A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations. However, since each product term cluster is associated with a logic macrocell, the logic macrocell can be individually configured for asynchronous operation by simply disconnecting the appropriate product term from the product term cluster and using the product term for the desired asynchronous function. Thus, a single PLD built using the programmable logic block cells supports simultaneously synchronous and asynchronous operations.

摘要翻译： 可编程逻辑器件（PLD）单元用于构建高密度高性能可编程逻辑器件（PLD）。 PLD单元包括两个可编程逻辑块单元。 PLD单元还包括I / O单元和输入宏单元。 此外，PLD单元包括可编程输出开关矩阵组的子组和可编程输入开关矩阵组的子组。 每个可编程逻辑块单元包括多个乘积项。 集群中至少有一个产品术语可编程地可用于集群。 当产品术语与集群断开连接时，产品术语用于控制逻辑宏单元输出信号或异步功能的极性。 因此，可编程可连接产品术语可用于同步或异步操作。 如果可编程可连接和可断开的产品术语连接到产品术语集群，则可编程逻辑块单元用于同步操作。 然而，由于每个产品项集合与逻辑宏单元相关联，所以逻辑宏单元可以通过简单地从产品项集群中断开适当的产品项并使用所需的异步功能的乘积项来单独配置用于异步操作。 因此，使用可编程逻辑块单元构建的单个PLD同时支持同步和异步操作。