公开(公告)号：US07327159B1

公开(公告)日：2008-02-05

申请号：US11287720

申请日：2005-11-28

申请人： Om P. Agrawal ,  Ravindar M. Lall ,  David L. Rutledge ,  Tom Gustafson

发明人： Om P. Agrawal ,  Ravindar M. Lall ,  David L. Rutledge ,  Tom Gustafson

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： In accordance with an embodiment of the present invention, a programmable logic device includes a memory adapted to store information in the programmable logic device, an input/output circuit adapted to transfer information into or out of the programmable logic device, and an interconnect architecture adapted to route information within the programmable logic device. An interface circuit is provided to couple the memory and the input/output circuit to the interconnect architecture.

摘要翻译： 根据本发明的实施例，可编程逻辑器件包括适于在可编程逻辑器件中存储信息的存储器，适于将信息传入或传出可编程逻辑器件的输入/输出电路，以及适配器 以在可编程逻辑器件内路由信息。 提供接口电路以将存储器和输入/输出电路耦合到互连体系结构。

公开(公告)号：US07427874B1

公开(公告)日：2008-09-23

申请号：US11949454

申请日：2007-12-03

申请人： Om P. Agrawal ,  Ravindar M. Lall ,  David L. Rutledge ,  Tom Gustafson

发明人： Om P. Agrawal ,  Ravindar M. Lall ,  David L. Rutledge ,  Tom Gustafson

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： A programmable logic device in accordance with an embodiment of the invention includes configurable logic blocks, embedded random access memory (RAM) blocks, and input/output blocks adapted to transfer information into or out of the programmable logic device. An interconnect architecture is adapted to route information among the configurable logic blocks, embedded RAM blocks, and input/output blocks within the programmable logic device. An interface block is provided that couples an embedded RAM block and an input/output block but not a logic block to the interconnect architecture.

摘要翻译： 根据本发明实施例的可编程逻辑器件包括可配置逻辑块，嵌入式随机存取存储器（RAM）块和适于将信息传入或传出可编程逻辑器件的输入/输出块。 互连架构适于在可编程逻辑器件内的可配置逻辑块，嵌入式RAM块和输入/输出块之间路由信息。 提供了将嵌入式RAM块和输入/输出块而不是逻辑块耦合到互连体系结构的接口块。

公开(公告)号：US07957208B1

公开(公告)日：2011-06-07

申请号：US12389149

申请日：2009-02-19

申请人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

发明人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

IPC分类号： G11C7/00

CPC分类号： H03K19/17772 ,  G11C29/028 ,  H03K19/1776

摘要： In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

摘要翻译： 在一个实施例中，可编程逻辑器件包括多个逻辑块; 多个输入/输出块; 易失性配置存储器，其适于存储用于配置逻辑块和输入/输出块的配置数据; 适用于存储用户数据的嵌入式块RAM; 闪存具有至少第一分区和第二分区; 以及适于提供对所述非易失性存储器的所述第一分区的外部设备访问的数据端口。 闪存适于在数据端口内的第一分区用户数据内存储，并且还适于在第二分区用户内存储来自嵌入式块RAM的数据。

公开(公告)号：US07554358B1

公开(公告)日：2009-06-30

申请号：US11397985

申请日：2006-04-05

申请人： Fabiano Fontana ,  Henry Law ,  Howard Tang ,  Om P. Agrawal ,  David L. Rutledge

发明人： Fabiano Fontana ,  Henry Law ,  Howard Tang ,  Om P. Agrawal ,  David L. Rutledge

IPC分类号： H01L25/00

CPC分类号： H03K19/17772 ,  H03K19/1776

摘要： Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks, and a volatile memory to store data within the programmable logic device, with configuration memory adapted to store first configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory of the programmable logic device. The programmable logic device further includes a non-volatile memory adapted to store data provided from the volatile memory.

摘要翻译： 本文公开了系统和方法，以提供用于可编程逻辑器件的改进的非易失性存储技术。 例如，根据本发明的实施例，可编程逻辑器件包括多个逻辑块，多个输入/输出块和用于在可编程逻辑器件内存储数据的易失性存储器，配置存储器适于 存储用于配置逻辑块，输入/输出块和可编程逻辑器件的易失性存储器的第一配置数据。 可编程逻辑器件还包括适于存储从易失性存储器提供的数据的非易失性存储器。

公开(公告)号：US07459931B1

公开(公告)日：2008-12-02

申请号：US11398437

申请日：2006-04-05

申请人： Howard Tang ,  Henry Law ,  David L. Rutledge ,  Om P. Agrawal ,  Fabiano Fontana

发明人： Howard Tang ,  Henry Law ,  David L. Rutledge ,  Om P. Agrawal ,  Fabiano Fontana

IPC分类号： H03K19/177

CPC分类号： H03K19/17772 ,  H03K19/17744 ,  H03K19/1776

摘要： Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks, a volatile memory block, and configuration memory cells to store configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory block of the programmable logic device. The programmable logic device further includes circuit techniques for preventing loss of data stored in the volatile memory block due to a reconfiguration. Furthermore, for example, the programmable logic device may further prevent the loss of data stored in user registers or loss of input/output personality due to the reconfiguration.

摘要翻译： 本文公开了系统和方法以提供PLD的重新配置技术。 例如，根据本发明的实施例，可编程逻辑器件包括逻辑块，输入/输出块，易失性存储器块和配置存储器单元，以存储配置逻辑块的配置数据，输入/输出 块和可编程逻辑器件的易失性存储器块。 可编程逻辑器件还包括用于防止由于重新配置而存储在易失性存储器块中的数据丢失的电路技术。 此外，例如，可编程逻辑器件还可以防止由于重新配置而存储在用户寄存器中的数据的丢失或输入/输出个性的丢失。

公开(公告)号：US07378873B1

公开(公告)日：2008-05-27

申请号：US11446548

申请日：2006-06-02

申请人： Howard Tang ,  Om P. Agrawal ,  David L. Rutledge ,  Fabiano Fontana

发明人： Howard Tang ,  Om P. Agrawal ,  David L. Rutledge ,  Fabiano Fontana

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/17744

摘要： Systems and methods are disclosed herein to provide an improved approach to the configuration of integrated circuits such as programmable logic devices (PLDs). For example, in accordance with one embodiment of the present invention, a PLD includes volatile memory adapted to store configuration data to configure the PLD for its intended function. The PLD further includes non-volatile memory adapted to store configuration data which is transferable to the volatile memory to configure the PLD for its intended function. The PLD further includes a serial peripheral interface (SPI) port adapted to receive configuration data from an external device for transfer into one of the volatile memory and the non-volatile memory.

摘要翻译： 本文公开了系统和方法，以提供诸如可编程逻辑器件（PLD）之类的集成电路的配置的改进方法。 例如，根据本发明的一个实施例，PLD包括适于存储配置数据以便为其功能配置PLD的易失性存储器。 PLD还包括适于存储配置数据的非易失性存储器，其可转移到易失性存储器以根据其预期功能配置PLD。 PLD还包括串行外设接口（SPI）端口，适于从外部设备接收配置数据，以传输到易失性存储器和非易失性存储器之一。

公开(公告)号：US07495970B1

公开(公告)日：2009-02-24

申请号：US11446309

申请日：2006-06-02

申请人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

发明人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

IPC分类号： G11C7/10

CPC分类号： H03K19/17772 ,  G11C29/028 ,  H03K19/1776

摘要： Systems and methods provide non-volatile memory architectures for programmable logic devices. For example, a programmable logic device may include logic blocks, input/output blocks, and configuration memory to store configuration data for configuration of the logic blocks and the input/output blocks. A first non-volatile memory may store user information, besides configuration data, and a first port includes a dedicated serial peripheral interface to provide access to the first non-volatile memory.

摘要翻译： 系统和方法为可编程逻辑器件提供非易失性存储器架构。 例如，可编程逻辑器件可以包括逻辑块，输入/输出块和配置存储器，以存储用于配置逻辑块和输入/输出块的配置数据。 除了配置数据之外，第一非易失性存储器可以存储用户信息，并且第一端口包括用于提供对第一非易失性存储器的访问的专用串行外围接口。

公开(公告)号：US07579865B1

公开(公告)日：2009-08-25

申请号：US12186027

申请日：2008-08-05

申请人： David L. Rutledge ,  Wei Han ,  Yoshita Yerramilli

发明人： David L. Rutledge ,  Wei Han ,  Yoshita Yerramilli

IPC分类号： H03K19/173

CPC分类号： H03K19/1776 ,  H03K19/17764

摘要： In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data. A plurality of configuration memory cells within the PLD is adapted to receive configuration data transferred from the non-volatile memory. The PLD further includes control logic adapted to determine based on the logic states of the first and second bits stored in the non-volatile memory and prior to any transfer of the configuration data whether to transfer the configuration data from the non-volatile memory to the configuration memory cells.

摘要翻译： 在一个实施例中，诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）包括适于存储第一位，第二位和多个配置数据的非易失性存储器。 PLD内的多个配置存储器单元适于接收从非易失性存储器传送的配置数据。 PLD还包括控制逻辑，其适于基于存储在非易失性存储器中的第一和第二位的逻辑状态确定并且在配置数据的任何传送之前是否将配置数据从非易失性存储器传送到 配置存储单元。

公开(公告)号：US5245226A

公开(公告)日：1993-09-14

申请号：US661285

申请日：1991-02-25

申请人： Milton M. Hood, Jr. ,  David L. Rutledge ,  Kapil Shankar ,  Rudolf Usselmann

发明人： Milton M. Hood, Jr. ,  David L. Rutledge ,  Kapil Shankar ,  Rudolf Usselmann

IPC分类号： H03K19/173

CPC分类号： H03K19/1737

摘要： A macrocell is provided for use in logic circuits which is capable of being configured into any one of six different states so as to replicate an X-type output architecture, an L-type output architecture and a number of hybrid architectures which encompass features from one or both of these types.

摘要翻译： 宏单元被提供用于能够被配置成六种不同状态中的任何一种的逻辑电路中，以便复制X型输出架构，L型输出架构和多个混合体系结构，其中包含一个 或这两种类型。

公开(公告)号：US4761768A

公开(公告)日：1988-08-02

申请号：US707662

申请日：1985-03-04

申请人： John E. Turner ,  David L. Rutledge

发明人： John E. Turner ,  David L. Rutledge

IPC分类号： G11C17/00 ,  G01R31/3185 ,  G11C16/02 ,  G11C16/04 ,  H01L21/82 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H03K19/173 ,  H03K19/177 ,  G06F11/26

CPC分类号： H03K19/1736 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/17776 ,  H03K19/1778

摘要： An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. The PLD includes a serial register latch (SRL) which is coupled to the product terms of the PLD array. Input programming data for a selected row of the array is serially entered into the SRL, and during a programming cycle the SRL data is employed to simultaneously program the storage elements of the selected row to either the enhancement mode or the depletion mode. The data programmed into the array may be verified at high speed. The status of each of the cells in the selected row can be sensed using the normal sense amplifiers and loaded into the SRL in parallel, and thereafter serially shifted out of the PLD for external verification. The PLD output logic and sense amplifiers can be functionally validated independent of the data in the array. Test data such as apparent array patterns are serially loaded into the SRL, and thereafter forced onto the normal sense amplifier inputs, propagated through the output logic and read out of the device output pin.

摘要翻译： 公开了一种改进的可编程逻辑器件（PLD），其采用可以高速编程和擦除的电可擦除存储器单元。 PLD存储单元包括作为存储元件的浮栅晶体管，其由Fowler-Nordheim隧道编程和擦除。 PLD包括串行寄存器锁存器（SRL），其耦合到PLD阵列的产品项。 串行选择行的输入编程数据被串行输入到SRL中，并且在编程周期期间，使用SRL数据来同时将所选行的存储元件编程为增强模式或耗尽模式。 可以高速验证编程到阵列中的数据。 所选行中的每个单元的状态可以使用正常读出放大器并行并入到SRL中，然后从PLD中串行移出外部验证。 PLD输出逻辑和读出放大器可以独立于阵列中的数据进行功能验证。 诸如表观阵列图案的测试数据被串行地加载到SRL中，然后被强制到正常读出放大器输入端，通过输出逻辑传播并从器件输出引脚读出。