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    Flexible memory architectures for programmable logic devices
    1.
    发明授权
    Flexible memory architectures for programmable logic devices 有权
    用于可编程逻辑器件的灵活存储器架构

    公开(公告)号：US07495970B1

    公开(公告)日：2009-02-24

    申请号：US11446309

    申请日：2006-06-02

    申请人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

    发明人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

    IPC分类号： G11C7/10

    CPC分类号： H03K19/17772 ,  G11C29/028 ,  H03K19/1776

    摘要： Systems and methods provide non-volatile memory architectures for programmable logic devices. For example, a programmable logic device may include logic blocks, input/output blocks, and configuration memory to store configuration data for configuration of the logic blocks and the input/output blocks. A first non-volatile memory may store user information, besides configuration data, and a first port includes a dedicated serial peripheral interface to provide access to the first non-volatile memory.

    摘要翻译： 系统和方法为可编程逻辑器件提供非易失性存储器架构。 例如，可编程逻辑器件可以包括逻辑块，输入/输出块和配置存储器，以存储用于配置逻辑块和输入/输出块的配置数据。 除了配置数据之外，第一非易失性存储器可以存储用户信息，并且第一端口包括用于提供对第一非易失性存储器的访问的专用串行外围接口。

    Programmable logic devices with user non-volatile memory
    2.
    发明授权
    Programmable logic devices with user non-volatile memory 有权
    具有用户非易失性存储器的可编程逻辑器件

    公开(公告)号：US07554358B1

    公开(公告)日：2009-06-30

    申请号：US11397985

    申请日：2006-04-05

    申请人： Fabiano Fontana ,  Henry Law ,  Howard Tang ,  Om P. Agrawal ,  David L. Rutledge

    发明人： Fabiano Fontana ,  Henry Law ,  Howard Tang ,  Om P. Agrawal ,  David L. Rutledge

    IPC分类号： H01L25/00

    CPC分类号： H03K19/17772 ,  H03K19/1776

    摘要： Systems and methods are disclosed herein to provide improved non-volatile storage techniques for programmable logic devices. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of logic blocks, a plurality of input/output blocks, and a volatile memory to store data within the programmable logic device, with configuration memory adapted to store first configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory of the programmable logic device. The programmable logic device further includes a non-volatile memory adapted to store data provided from the volatile memory.

    摘要翻译： 本文公开了系统和方法，以提供用于可编程逻辑器件的改进的非易失性存储技术。 例如，根据本发明的实施例，可编程逻辑器件包括多个逻辑块，多个输入/输出块和用于在可编程逻辑器件内存储数据的易失性存储器，配置存储器适于 存储用于配置逻辑块，输入/输出块和可编程逻辑器件的易失性存储器的第一配置数据。 可编程逻辑器件还包括适于存储从易失性存储器提供的数据的非易失性存储器。

    Programmable logic devices with transparent field reconfiguration
    3.
    发明授权
    Programmable logic devices with transparent field reconfiguration 有权
    具有透明场重构功能的可编程逻辑器件

    公开(公告)号：US07459931B1

    公开(公告)日：2008-12-02

    申请号：US11398437

    申请日：2006-04-05

    申请人： Howard Tang ,  Henry Law ,  David L. Rutledge ,  Om P. Agrawal ,  Fabiano Fontana

    发明人： Howard Tang ,  Henry Law ,  David L. Rutledge ,  Om P. Agrawal ,  Fabiano Fontana

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17772 ,  H03K19/17744 ,  H03K19/1776

    摘要： Systems and methods are disclosed herein to provide reconfiguration techniques for PLDs. For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks, a volatile memory block, and configuration memory cells to store configuration data for configuration of the logic blocks, the input/output blocks, and the volatile memory block of the programmable logic device. The programmable logic device further includes circuit techniques for preventing loss of data stored in the volatile memory block due to a reconfiguration. Furthermore, for example, the programmable logic device may further prevent the loss of data stored in user registers or loss of input/output personality due to the reconfiguration.

    摘要翻译： 本文公开了系统和方法以提供PLD的重新配置技术。 例如，根据本发明的实施例，可编程逻辑器件包括逻辑块，输入/输出块，易失性存储器块和配置存储器单元，以存储配置逻辑块的配置数据，输入/输出 块和可编程逻辑器件的易失性存储器块。 可编程逻辑器件还包括用于防止由于重新配置而存储在易失性存储器块中的数据丢失的电路技术。 此外，例如，可编程逻辑器件还可以防止由于重新配置而存储在用户寄存器中的数据的丢失或输入/输出个性的丢失。

    Flexible memory architectures for programmable logic devices
    4.
    发明授权
    Flexible memory architectures for programmable logic devices 有权
    用于可编程逻辑器件的灵活存储器架构

    公开(公告)号：US07957208B1

    公开(公告)日：2011-06-07

    申请号：US12389149

    申请日：2009-02-19

    申请人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

    发明人： Howard Tang ,  Fabiano Fontana ,  David L. Rutledge ,  Om P. Agrawal ,  Henry Law

    IPC分类号： G11C7/00

    CPC分类号： H03K19/17772 ,  G11C29/028 ,  H03K19/1776

    摘要： In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

    摘要翻译： 在一个实施例中，可编程逻辑器件包括多个逻辑块; 多个输入/输出块; 易失性配置存储器，其适于存储用于配置逻辑块和输入/输出块的配置数据; 适用于存储用户数据的嵌入式块RAM; 闪存具有至少第一分区和第二分区; 以及适于提供对所述非易失性存储器的所述第一分区的外部设备访问的数据端口。 闪存适于在数据端口内的第一分区用户数据内存储，并且还适于在第二分区用户内存储来自嵌入式块RAM的数据。

    High speed CMOS output buffer circuit minimizes propagation delay and crowbar current
    5.
    发明授权
    High speed CMOS output buffer circuit minimizes propagation delay and crowbar current 失效
    高速CMOS输出缓冲电路可最大限度地减少传播延迟和消弧电流

    公开(公告)号：US5438278A

    公开(公告)日：1995-08-01

    申请号：US128628

    申请日：1993-09-28

    申请人： Jack T. Wong ,  Fabiano Fontana ,  Henry Law

    发明人： Jack T. Wong ,  Fabiano Fontana ,  Henry Law

    IPC分类号： H03K17/0412 ,  H03K17/16 ,  H03K19/0175

    CPC分类号： H03K17/164 ,  H03K17/04123

    摘要： An output buffer circuit is disclosed that minimizes propagation delay and crowbar current. This circuit receives a data input signal and provides an output signal. This circuit includes a pull-up transistor, a first pull-down transistor, a speed improvement circuit and a crowbar current reduction circuit. The speed improvement circuit comprises an inverter with small propagation delay coupled to a second pull-down transistor which is smaller than the first pull-down transistor. The speed improvement circuit minimizes the propagation delay of the circuit when the data input signals changes from a high logic level to a low logic level by speeding up the initial rate of fall of the output signal due to the fast turning on of the second small pull-down transistor which receives the data input signal quickly through the small-propagation-delay inverter. The crowbar current reduction circuit comprises a first crowbar current reduction transistor which is smaller than the pull-up transistor. The crowbar current reduction circuit minimizes the crowbar current through the pull-up transistor and the first pull-down transistor when the data input signals changes from a high logic level to a low logic level by speeding up the turning off of the pull-up transistor due to the fast turning on of the small first crowbar current reduction transistor which receives the data input signal quickly through the small-propagation-delay inverter. A split Ground metal bus and a split package lead are used for minimizing noise.

    摘要翻译： 公开了一种输出缓冲器电路，其最小化传播延迟和消弧电流。 该电路接收数据输入信号并提供输出信号。 该电路包括上拉晶体管，第一下拉晶体管，速度改善电路和急流电流降低电路。 速度改进电路包括耦合到比第一下拉晶体管小的第二下拉晶体管的传播延迟小的逆变器。 当数据输入信号从高逻辑电平变化到低逻辑电平时，速度提高电路使电路的传播延迟最小化，由于第二小拉的快速接通而加速输出信号的初始下降速率 通过小型传播延迟逆变器快速接收数据输入信号。 撬棒电流降低电路包括小于上拉晶体管的第一扼流圈电流减小晶体管。 当数据输入信号从高逻辑电平变为低逻辑电平时，通过加速上拉晶体管的截止，撬棒电流降低电路使通过上拉晶体管和第一下拉晶体管的撬棒电流最小化 由于通过小传播延迟逆变器快速接收数据输入信号的小的第一短路电流减小晶体管的快速导通。 分体接地金属总线和分体封装引线用于使噪声最小化。

    High speed NOR gate with small output voltage swings
    6.
    发明授权
    High speed NOR gate with small output voltage swings 失效
    高速NOR门，输出电压波动小

    公开(公告)号：US5432463A

    公开(公告)日：1995-07-11

    申请号：US138303

    申请日：1993-10-15

    申请人： Jack T. Wong ,  Fabiano Fontana ,  Henry Law

    发明人： Jack T. Wong ,  Fabiano Fontana ,  Henry Law

    IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0948 ,  H03K17/30

    CPC分类号： H03K19/0948 ,  H03K19/00384 ,  H03K19/01707

    摘要： A high speed multiple input NOR gate. In an illustrative embodiment, the invention includes a plurality of pull-down transistors for providing an output signal. A pull-up transistor is coupled to the plurality of pull-down transistors for providing a drive current. A regulator is coupled to the pull-up transistor for regulating the drive current in response to temperature and power supply voltage variation so as to maintain the speed of the output signal during a low-to-high transition of the output signal. In specific implementations, the NOR gate is designed to regulate the output signal so that a high level or a low level thereof is maintained at a predetermined level. The several embodiments disclosed provide: 1) a high speed NOR gate that offers high speed performance on both the low-to-high and high-to-low transitions; 2) a high speed NOR gate for which voltage swings on the input circuits thereof are minimal; 3) a high speed NOR gate with pull-up current temperature and voltage compensation for improved performance on the low-to-high transition of the output; and 4) a high speed NOR gate using a feedback technique to regulate and limit the logic low voltage on the output such that this level has minimal variation independent of the number of the NOR inputs held in the logic high state.

    摘要翻译： 高速多输入NOR门。 在说明性实施例中，本发明包括用于提供输出信号的多个下拉晶体管。 上拉晶体管耦合到多个下拉晶体管，用于提供驱动电流。 调节器耦合到上拉晶体管，用于响应于温度和电源电压变化来调节驱动电流，以便在输出信号的低到高转换期间保持输出信号的速度。 在具体实现中，NOR门被设计成调节输出信号，使得其高电平或低电平保持在预定电平。 所公开的几个实施例提供：1）高速或非门，其在低到高和高到低的转换时都提供高速性能; 2）高速NOR门，其输入电路上的电压摆幅最小; 3）具有上拉电流温度和电压补偿的高速NOR门，用于在输出的低到高转换时提高性能; 和4）高速NOR门，其使用反馈技术来调节和限制输出上的逻辑低电压，使得该电平具有独立于保持在逻辑高状态中的NOR输入的数量的最小变化。

    Method and apparatus for data re-arrangement
    8.
    发明授权
    Method and apparatus for data re-arrangement 有权
    数据重新安排的方法和装置

    公开(公告)号：US07769247B2

    公开(公告)日：2010-08-03

    申请号：US10448717

    申请日：2003-05-30

    申请人： Daniel Wong ,  Henry Law

    发明人： Daniel Wong ,  Henry Law

    IPC分类号： G06K9/32 ,  G06K9/36 ,  G09G5/00 ,  H04N9/74

    CPC分类号： G06T15/005

    摘要： A method and method and apparatus for data re-arrangement includes the steps of receiving output pixel coordinates (X, Y) and obtaining an input pixel offset value (ΔS, ΔT), wherein the output pixel coordinate represents a location for a two dimensional matrix. The input pixel offset value is obtained in reference to initial input pixel coordinates (S, T) which may be received with the output pixel coordinates or calculated based on the input and/or output pixel coordinates. The input pixel offset value may be any type of representation that provides for a delta value, for example, (ΔS, ΔT) may represent a shift representation for the offset within a matrix array. The method and apparatus for data re-arrangement further includes retrieving an input pixel based on the initial input pixel coordinates and the offset value.

    摘要翻译： 一种用于数据重新排列的方法和方法和装置包括以下步骤：接收输出像素坐标（X，Y）并获得输入像素偏移值（＆Dgr; S，＆Dgr; T），其中输出像素坐标表示 二维矩阵。 参考初始输入像素坐标（S，T）获得输入像素偏移值，该坐标可以用输出像素坐标接收或基于输入和/或输出像素坐标计算。 输入像素偏移值可以是提供增量值的任何类型的表示，例如，（＆Dgr; S，＆Dgr; T）可以表示矩阵阵列内的偏移的移位表示。 用于数据重新排列的方法和装置还包括基于初始输入像素坐标和偏移值检索输入像素。

    Programmable logic device with power-saving architecture
    9.
    发明授权
    Programmable logic device with power-saving architecture 有权
    具有省电架构的可编程逻辑器件

    公开(公告)号：US07558143B1

    公开(公告)日：2009-07-07

    申请号：US12100859

    申请日：2008-04-10

    申请人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

    发明人： Henry Law ,  Brad Sharpe-Geisler ,  Giap Tran ,  Kiet Truong ,  Bai Nguyen

    IPC分类号： G11C5/14

    CPC分类号： H03K19/17772 ,  G11C5/144 ,  H03K19/1776 ,  H03K19/17784

    摘要： A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment, the PLD includes a switch such as an internal power supply operable to provide power to the logic core of the PLD, such as the programmable logic blocks, routing structure, and volatile configuration memory. The internal power supply powers down the logic core in response to assertion of a power-down signal, while power is maintained to other circuitry of the PLD.

    摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有掉电操作模式，其降低了用于PLD的待机或空闲周期期间的功耗。 在一个实施例中，PLD包括可操作以向PLD的逻辑核心（诸如可编程逻辑块，路由结构和易失性配置存储器）提供电力的诸如内部电源的开关。 内部电源响应于断电信号的断言而使逻辑内核断电，同时将功率保持在PLD的其他电路。

    Video playback method and apparatus
    10.
    发明授权
    Video playback method and apparatus 有权
    视频播放方法和装置

    公开(公告)号：US07463819B2

    公开(公告)日：2008-12-09

    申请号：US10976949

    申请日：2004-10-29

    申请人： Henry Law ,  Kenneth Man ,  Peter Cao

    发明人： Henry Law ,  Kenneth Man ,  Peter Cao

    IPC分类号： H04N7/26

    CPC分类号： G09G5/008 ,  G09G3/3648 ,  G09G5/399 ,  G09G2320/0252 ,  G09G2360/02

    摘要： A video playback circuit receives flip call information and vertical synchronization information, and in response determines a pause mode and a playback mode. Flip call information, as is known in the art, provides an indication for flipping between a front buffer and a back buffer, in order to facilitate rendering into one buffer while rasterizing out of the other buffer. Vertical synchronization information describes the completion of rasterizing an image onto a display, and often occurs at periodic intervals, e.g., 60 Hz, 100 Hz. The video playback circuit further includes a pause/playback-based frame buffer pointer information generator. The pause/playback-based frame buffer pointer information generator generates unfiltered frame buffer pointer information when in the pause mode. Otherwise, the pause/playback-based frame buffer pointer information generator generates filtered frame buffer pointer information when in the playback mode. The unfiltered frame buffer pointer information indicates rasterization of unfiltered rasterization data from the frame buffer during the pause mode. Similarly, the filtered frame buffer pointer information indicates rasterization of filtered rasterization data from the frame buffer when in the playback mode.

    摘要翻译： 视频播放电路接收翻转呼叫信息和垂直同步信息，并且响应于确定暂停模式和播放模式。 如本领域已知的翻转呼叫信息提供了用于在前缓冲器和后缓冲器之间翻转的指示，以便于在从另一个缓冲器中进行光栅化时便于呈现为一个缓冲器。 垂直同步信息描述了将图像光栅化到显示器上的完成，并且经常以周期性间隔（例如，60Hz，100Hz）发生。 视频回放电路还包括基于暂停/重放的帧缓冲器指针信息发生器。 当处于暂停模式时，基于暂停/重放的帧缓冲器指针信息发生器生成未过滤的帧缓冲器指针信息。 否则，当处于播放模式时，基于暂停/重放的帧缓冲器指针信息发生器产生滤波的帧缓冲器指针信息。 未过滤的帧缓冲器指针信息指示在暂停模式期间来自帧缓冲器的未滤波光栅化数据的光栅化。 类似地，经过滤波的帧缓冲器指针信息表示当处于回放模式时从帧缓冲器中滤波的光栅化数据的光栅化。