公开(公告)号：US09954540B1

公开(公告)日：2018-04-24

申请号：US15462514

申请日：2017-03-17

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols ,  Changku Hwang ,  Nicolas M. Huynh ,  Daniel S. Woo

IPC: H03L7/099 ,  H03L7/081 ,  H03L5/00 ,  H03L7/07

CPC classification number: H03L7/07 ,  H03L7/0995

Abstract: A system that generates a click signal includes a first digitally controlled oscillator (DCO) having a first fundamental frequency, and a second DCO having a second fundamental frequency. The system also includes a Muller C-element, which combines outputs of the first and second DCOs to produce the clock signal, which feeds back into the first and second DCOs. During a calibration operation, while the second DCO is set to a frequency larger than the target frequency, the system adjusts the first DCO with reference to a first feedback loop, which includes the first DCO, so that the clock signal matches the target frequency, and while the first DCO is set to the adjusted first fundamental frequency plus a frequency offset, the system adjusts the second DCO with reference to a second feedback loop, which includes the second DCO, so that the clock signal matches the target frequency.

公开(公告)号：US09312864B2

公开(公告)日：2016-04-12

申请号：US14498744

申请日：2014-09-26

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols ,  Changku Hwang ,  Daniel S. Woo

IPC: H03K3/03 ,  H03L7/08 ,  H03L7/099 ,  H03L7/00

CPC classification number: H03L7/0802 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H03L7/0991

Abstract: In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.

Abstract translation: 在提供时钟信号的集成电路中，非对称频率锁相环（AFLL）包括输出具有第一基频的第一信号的第一数字控制振荡器（DCO）和输出具有第一基频的第二信号的第二DCO， 第二基频。 集成电路包括向第二DCO提供电源电压的电压调节器。 此外，AFLL包括基于电源电压和平均电源电压的瞬时值来选择第一DCO和第二DCO中的一个的控制逻辑。 此外，AFLL基于电源电压的瞬时值和平均电源电压来调整第一子锁频环路中所选DCO的增益。 以这种方式，降低了集成电路中电源电压变化对时间关键路径的影响。

公开(公告)号：US20150365093A1

公开(公告)日：2015-12-17

申请号：US14498744

申请日：2014-09-26

Applicant: Oracle International Corporation

Inventor： Yifan YangGong ,  Sebastian Turullols ,  Changku Hwang ,  Daniel S. Woo

IPC: H03L7/08 ,  H03L7/099

CPC classification number: H03L7/0802 ,  H03L7/00 ,  H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H03L7/0991

Abstract: In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.

Abstract translation: 在提供时钟信号的集成电路中，非对称频率锁相环（AFLL）包括输出具有第一基频的第一信号的第一数字控制振荡器（DCO）和输出具有第一基频的第二信号的第二DCO， 第二基频。 集成电路包括向第二DCO提供电源电压的电压调节器。 此外，AFLL包括基于电源电压和平均电源电压的瞬时值来选择第一DCO和第二DCO中的一个的控制逻辑。 此外，AFLL基于电源电压的瞬时值和平均电源电压来调整第一子锁频环路中所选DCO的增益。 以这种方式，降低了集成电路中电源电压变化对时间关键路径的影响。