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    APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
    2.
    发明申请
    APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
    低速延迟加速器的装置和方法

    公开(公告)号：US20170017491A1

    公开(公告)日：2017-01-19

    申请号：US15281944

    申请日：2016-09-30

    申请人： Oren Ben-Kiki ,  ILAN PARDO ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

    发明人： Oren Ben-Kiki ,  ILAN PARDO ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

    IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F9/30

    CPC分类号： G06F9/3802 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F9/54 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0772 ,  G06F12/0875 ,  G06F2212/452

    摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.

    摘要翻译： 描述了一种用于提供加速器的低延迟调用的装置和方法。 例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功执行命令，则一个或多个加速器将存储包括 结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断 其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

    APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
    4.
    发明申请
    APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
    低速延迟加速器的装置和方法

    公开(公告)号：US20160246597A1

    公开(公告)日：2016-08-25

    申请号：US15145748

    申请日：2016-05-03

    申请人： Oren Ben-Kiki ,  llan Pardo ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

    发明人： Oren Ben-Kiki ,  llan Pardo ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3802 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F9/54 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0772 ,  G06F12/0875 ,  G06F2212/452

    摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.

    摘要翻译： 描述了一种用于提供加速器的低延迟调用的装置和方法。 例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据并响应于尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功地执行命令，则一个或多个加速器将存储包括 结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断 其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

    APPARATUS AND METHOD FOR TASK-SWITCHABLE SYNCHRONOUS HARDWARE ACCELERATORS
    5.
    发明申请
    APPARATUS AND METHOD FOR TASK-SWITCHABLE SYNCHRONOUS HARDWARE ACCELERATORS 审中-公开
    用于可切换同步硬件加速器的设备和方法

    公开(公告)号：US20140189333A1

    公开(公告)日：2014-07-03

    申请号：US13730143

    申请日：2012-12-28

    申请人： Oren Ben-Kiki ,  Ilan Pardo ,  Eliezer Weissmann

    发明人： Oren Ben-Kiki ,  Ilan Pardo ,  Eliezer Weissmann

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F9/30054 ,  G06F9/30189 ,  G06F9/3881

    摘要： A processor comprising: execution logic to execute a first thread including an accelerator invocation instruction to invoke an accelerator command; an accelerator to execute an accelerator thread in response to the accelerator command, the accelerator to store state data associated with the accelerator thread in a application memory area in memory, wherein prior to executing the accelerator thread, the accelerator is to lock entries in a translation lookaside buffer (TLB) associated with the accelerator thread to prevent an exception which might otherwise result.

    摘要翻译： 一种处理器，包括执行逻辑，以执行包括调用加速器命令的加速器调用指令的第一线程; 加速器，其响应于加速器命令执行加速器线程，加速器，用于将与加速器线程相关联的状态数据存储在存储器中的应用存储器区域中，其中在执行加速器线程之前，加速器将锁定条目转换为 与加速器线程相关联的后备缓冲器（TLB），以防止否则可能导致的异常。