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    APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
    2.
    发明申请
    APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS 审中-公开
    低速延迟加速器的装置和方法

    公开(公告)号：US20170017491A1

    公开(公告)日：2017-01-19

    申请号：US15281944

    申请日：2016-09-30

    申请人： Oren Ben-Kiki ,  ILAN PARDO ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

    发明人： Oren Ben-Kiki ,  ILAN PARDO ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

    IPC分类号： G06F9/38 ,  G06F12/0875 ,  G06F9/30

    CPC分类号： G06F9/3802 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/3881 ,  G06F9/54 ,  G06F11/0721 ,  G06F11/0724 ,  G06F11/0772 ,  G06F12/0875 ,  G06F2212/452

    摘要： An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a command register for storing command data identifying a command to be executed; a result register to store a result of the command or data indicating a reason why the commend could not be executed; execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying the command within the command register; one or more accelerators to read the command data from the command register and responsively attempt to execute the command identified by the command data, wherein if the one or more accelerators successfully execute the command, the one or more accelerators are to store result data comprising the results of the command in the result register; and if the one or more accelerators cannot successfully execute the command, the one or more accelerators are to store result data indicating a reason why the command cannot be executed, wherein the execution logic is to temporarily halt execution until the accelerator completes execution or is interrupted, wherein the accelerator includes logic to store its state if interrupted so that it can continue execution at a later time.

    摘要翻译： 描述了一种用于提供加速器的低延迟调用的装置和方法。 例如，根据一个实施例的处理器包括：命令寄存器，用于存储标识要执行的命令的命令数据; 用于存储命令结果的结果寄存器或指示不能执行推荐的原因的数据; 执行逻辑以执行包括用于调用一个或多个加速器命令的加速器调用指令的多个指令，所述加速器调用指令将指定所述命令的命令数据存储在所述命令寄存器内; 一个或多个加速器，用于从命令寄存器读取命令数据，并且响应地尝试执行由命令数据识别的命令，其中如果一个或多个加速器成功执行命令，则一个或多个加速器将存储包括 结果寄存器中的命令结果; 并且如果一个或多个加速器不能成功地执行命令，则一个或多个加速器将存储指示不能执行该命令的原因的结果数据，其中执行逻辑将暂停执行，直到加速器完成执行或被中断 其中所述加速器包括用于存储其状态的逻辑，如果被中断，使得其可以在稍后的时间继续执行。

    Snoop filter having centralized translation circuitry and shadow tag array
    3.
    发明授权
    Snoop filter having centralized translation circuitry and shadow tag array 有权
    具有集中翻译电路和阴影标签阵列的窥探滤波器

    公开(公告)号：US09268697B2

    公开(公告)日：2016-02-23

    申请号：US13730956

    申请日：2012-12-29

    申请人： Ilan Pardo ,  Niranjan Cooray ,  Stanislav Shwartsman ,  Shlomo Raikin

    发明人： Ilan Pardo ,  Niranjan Cooray ,  Stanislav Shwartsman ,  Shlomo Raikin

    IPC分类号： G06F12/08 ,  G06F12/10

    CPC分类号： G06F12/0822 ,  G06F12/0831 ,  G06F12/1027 ,  G06F12/1063

    摘要： A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.

    摘要翻译： 描述了包括多个处理核的处理器。 处理器包括耦合到每个所述处理核心的互连网络。 处理器包括连接到互连网络并与处理器的相干平面逻辑电路相关联的窥探滤波器逻辑电路。 监听滤波器逻辑电路包含用于保存信息的电路，该信息不仅识别哪个处理核心缓存由处理核心高速缓存的特定高速缓存线，而且在处理核心的高速缓存中缓存高速缓存行被缓存。

    APPARATUS AND METHOD FOR MEMORY-MAPPED REGISTER CACHING
    4.
    发明申请
    APPARATUS AND METHOD FOR MEMORY-MAPPED REGISTER CACHING 有权
    用于记忆映射寄存器缓存的装置和方法

    公开(公告)号：US20140189191A1

    公开(公告)日：2014-07-03

    申请号：US13730030

    申请日：2012-12-28

    申请人： Ilan Pardo ,  Michael Behar ,  Oren Ben-Kiki ,  Dror Markovich

    发明人： Ilan Pardo ,  Michael Behar ,  Oren Ben-Kiki ,  Dror Markovich

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0802 ,  G06F12/0875 ,  G06F12/0897 ,  Y02D10/13

    摘要： A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region within a level 1 (L1) data cache, and a data location table (DLT) to store data indicating a location of each architectural register within the register file cache and/or the architectural register region within the L1 data cache.

    摘要翻译： 描述了一种处理器，包括：实现为级别1（L1）数据高速缓存中的寄存器文件高速缓存和架构寄存器区域的组合的架构寄存器文件，以及数据位置表（DLT），用于存储指示每个 寄存器文件缓存内的架构寄存器和/或L1数据高速缓存内的体系结构寄存器区域。

    Compression format for high bandwidth dictionary compression
    6.
    发明授权
    Compression format for high bandwidth dictionary compression 有权
    高带宽字典压缩的压缩格式

    公开(公告)号：US08665124B2

    公开(公告)日：2014-03-04

    申请号：US13638147

    申请日：2011-10-01

    申请人： Ilan Pardo ,  Ido Y. Soffair ,  Dror Reif ,  Debendra Das Sharma ,  Akshay G. Pethe

    发明人： Ilan Pardo ,  Ido Y. Soffair ,  Dror Reif ,  Debendra Das Sharma ,  Akshay G. Pethe

    IPC分类号： H03M7/00

    CPC分类号： H03M7/3059 ,  H03M7/3088

    摘要： Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

    摘要翻译： 使用基于字典的高带宽无损压缩的方法，装置和系统。 具有同步和编码以支持压缩和解压缩操作的条目的一对字典通过压缩器和解压缩器的逻辑来实现。 压缩器/解压缩器逻辑操作以协作的方式，包括实现相同的字典更新方案，导致相应词典中的数据被同步。 字典还配置有可替换条目，并且替换策略基于通过链接传送的数据集合中的数据的匹配字节来实现。 公开了用于条目替换的各种方案以及延迟字典更新技术。 该技术支持使用并行操作的线速压缩和解压缩，从而实质上无延迟开销。

    METHOD AND APPARATUS FOR HIGH BANDWIDTH DICTIONARY COMPRESSION TECHNIQUE USING DELAYED DICTIONARY UPDATE
    9.
    发明申请
    METHOD AND APPARATUS FOR HIGH BANDWIDTH DICTIONARY COMPRESSION TECHNIQUE USING DELAYED DICTIONARY UPDATE 有权
    使用延迟字典更新的高带宽字典压缩技术的方法和装置

    公开(公告)号：US20130086339A1

    公开(公告)日：2013-04-04

    申请号：US13638130

    申请日：2011-10-01

    申请人： Ilan Pardo ,  Ido Y. Soffair ,  Dror Reif ,  Debendra Das Sharma ,  Akshay G. Pethe

    发明人： Ilan Pardo ,  Ido Y. Soffair ,  Dror Reif ,  Debendra Das Sharma ,  Akshay G. Pethe

    IPC分类号： G06F12/14

    CPC分类号： H03M7/30 ,  H03M7/3088

    摘要： Method, apparatus, and systems employing novel delayed dictionary update schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

    摘要翻译： 用于基于字典的高带宽无损压缩的新型延迟字典更新方案的方法，装置和系统。 具有同步和编码以支持压缩和解压缩操作的条目的一对字典通过压缩器和解压缩器的逻辑来实现。 压缩器/解压缩器逻辑操作以协作的方式，包括实现相同的字典更新方案，导致相应词典中的数据被同步。 字典还配置有可替换条目，并且替换策略基于通过链接传送的数据集合中的数据的匹配字节来实现。 公开了用于条目替换的各种方案以及延迟字典更新技术。 该技术支持使用并行操作的线速压缩和解压缩，从而实质上无延迟开销。