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公开(公告)号：US07460612B2
公开(公告)日：2008-12-02
申请号：US11203504
申请日：2005-08-11
IPC分类号： H04L27/00
CPC分类号： H03F3/24 , H03C3/40 , H03C5/00 , H03F2200/324 , H03F2200/331 , H03F2200/336 , H04K1/02 , H04L27/04 , H04L27/2092 , H04L27/365
摘要： A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.
摘要翻译： 一种用于复调制器的全数字正交架构的新型装置和方法。 复调制器可以替代现有的现有技术的模拟正交调制器结构和基于数字极坐标（r，θ）的那些。 调制器有效地作为复数数模转换器工作，其中数字输入以笛卡尔形式给出，即I和Q表示复数I + jQ，而输出是具有对应幅度和相移的调制RF信号 。 相移相对于由本地振荡器指定的参考相位，本地振荡器也被输入到转换器/调制器。 提供了包括具有双I和Q晶体管阵列的调制器，单个共享I / Q晶体管阵列，具有单端和差分输出的调制器以及具有单极性和双极性时钟和I / Q数据信号的调制器的几个实施例。
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公开(公告)号：US07463869B2
公开(公告)日：2008-12-09
申请号：US11115815
申请日：2005-04-26
IPC分类号： H04B1/04
CPC分类号： H04B1/0483 , H03F1/3241 , H03F1/3294 , H03F3/191 , H03F2200/331
摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.
摘要翻译： 一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。 增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。 发送缓冲器构造为NMOS开关阵列。 每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。 通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。 首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。 在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。
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公开(公告)号：US20080192876A1
公开(公告)日：2008-08-14
申请号：US12021205
申请日：2008-01-28
IPC分类号： H03D3/24
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal. The jitter is shifted to higher frequencies where it is filtered out by the PLL loop filter.
摘要翻译： 一种新颖有用的可变延迟数字控制晶体振荡器（DCXO）缓冲器（即切片器）。 在DCXO之后的常规限幅器被修改以将受控的随机可变延迟引入缓冲的DCXO时钟。 结果输出时钟信号然后被用作ADPLL电路的TDC的输入，以减轻由通过晶体管的LO / TX耦合引起的次谐波混合的劣化，并且减轻由于有限分辨率引起的死区效应 TDC。 介绍了将可变延迟引入到缓冲DCXO输出时钟信号中的两种机制：第一种在精细步骤中产生可变延迟的机制，以及在粗略步骤中产生可变延迟的第二种机制。 在这两种机制中，开关被合并到限幅器电路中，并使用可包括抖动信号的数字位序列进行控制。 开关通过改变切片器时钟输出的延迟的数字位序列被导通和关断，其用于移位所产生的输出时钟信号的上升和下降转换点。 抖动被转移到较高的频率，由PLL环路滤波器滤波。
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公开(公告)号：US07983375B2
公开(公告)日：2011-07-19
申请号：US12021205
申请日：2008-01-28
IPC分类号： H03D3/24
CPC分类号： H03L7/1806 , H03L2207/50
摘要： A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals. The switches are turned on and off via the digital bit sequences which varies the delay of the slicer clock output which serves to shift the rising and falling transition points of the resultant output clock signal. The jitter is shifted to higher frequencies where it is filtered out by the PLL loop filter.
摘要翻译： 一种新颖有用的可变延迟数字控制晶体振荡器（DCXO）缓冲器（即切片器）。 在DCXO之后的常规限幅器被修改以将受控的随机可变延迟引入缓冲的DCXO时钟。 结果输出时钟信号然后被用作ADPLL电路的TDC的输入，以减轻由通过晶体管的LO / TX耦合引起的次谐波混合的劣化，并且减轻由于有限分辨率引起的死区效应 TDC。 介绍了将可变延迟引入到缓冲DCXO输出时钟信号中的两种机制：第一种在精细步骤中产生可变延迟的机制，以及在粗略步骤中产生可变延迟的第二种机制。 在这两种机制中，开关被合并到限幅器电路中，并使用可包括抖动信号的数字位序列进行控制。 开关通过改变切片器时钟输出的延迟的数字位序列被导通和关断，其用于移位所产生的输出时钟信号的上升和下降转换点。 抖动被转移到较高的频率，由PLL环路滤波器滤波。
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