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公开(公告)号：US08493812B2
公开(公告)日：2013-07-23
申请号：US12913929
申请日：2010-10-28
IPC分类号： G11C8/08
CPC分类号： G11C5/145
摘要： A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable.
摘要翻译： 用于产生用于装置的可调升压电压的技术包括在充电阶段期间使用第一和第二开关将电容器充电到第一电压。 该技术还包括使用第三开关将第二电压堆叠在升压阶段的电容器两端的第一电压上以产生升压电压。 在这种情况下，升压电压仅在升压阶段被施加到器件的驱动电路，并且第一和第二电压中的至少一个是可调节的，从而使升压电压可调。
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2.发明授权Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory 失效不对称随机存取存储器单元，包括不对称存储单元的存储器和操作这种存储器的方法公开(公告)号：US07495949B2
公开(公告)日：2009-02-24
申请号：US11669369
申请日：2007-01-31
申请人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
发明人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory including such memory cells and to a method of operating such a memory.
摘要翻译： 包括交叉耦合的反相器（2,3）的非对称随机存取存储单元（1），它们通过一对互补位线的分开的位线（blt，blc）在它们的节点（22,32）处驱动，它们是 通过传输晶体管（21,31）连接，其中所述交叉耦合的反相器（2,3）具有不同的开关阈值并且表现出不对称的物理行为，其中附加的传输晶体管（4）串联地提供给一个通过 - 晶体管（21）在其中一个节点（22）和其专用位线（blc）之间。 此外，本发明涉及包括这种存储器单元的随机存取存储器以及操作这种存储器的方法。
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公开(公告)号：US20120155188A1
公开(公告)日：2012-06-21
申请号：US13284480
申请日：2011-10-28
CPC分类号： G11C7/18 , G11C7/12 , G11C29/846 , G11C2207/005
摘要： In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.
摘要翻译： 在可以并行访问的存储单元的阵列系统中降低功耗的电路中，本地评估电路连接到存储器单元阵列系统的存储单元和全局位线。 选择电路将全局位线分割成全局位线的上部和下部。 选择电路适于接收早期设定的预测信号，并且基于早期设定的预测信号将全局位线的上部连接到全局位线的下部。 早期设置的预测信号指示是否正在读取包括存储器单元的一组存储单元。 该电路还包括连接到全局位线的下部的N：1多路复用器，以接收全局位线的下部作为输入。
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4.发明申请Asymmetrical Random Access Memory Cell, Memory Comprising Asymmetrical Memory Cells And Method To Operate Such A Memory 失效非对称随机存取存储器单元，包含非对称存储单元的存储器和操作这样的存储器的方法公开(公告)号：US20070189061A1
公开(公告)日：2007-08-16
申请号：US11669369
申请日：2007-01-31
申请人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
发明人： Stefan Buettner , Torsten Mahnke , Wolfgang Penth , Otto Wagner
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory The invention relates to an asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (b1t, b1c) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory comprising such memory cells and to a method of operating such a memory.
摘要翻译： 不对称随机存取存储器单元，包括不对称存储器单元的存储器和用于操作这种存储器的方法本发明涉及一种非对称随机存取存储单元（1），包括交叉耦合的反相器（2,3），它们在其节点（22,32） ）通过一对互补位线的分开的位线（b 1 t，b 1 c），其经由传输晶体管（21,31）连接，其中所述交叉耦合的反相器（2,3）具有不同的 切换阈值并表现出不对称的物理行为，其中附加的传输晶体管（4）与节点（22）中的一个与其专用位线（blc）之间的一个传输晶体管（21）串联提供。 此外，本发明涉及包括这种存储器单元的随机存取存储器以及操作这种存储器的方法。
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公开(公告)号：US08422313B2
公开(公告)日：2013-04-16
申请号：US13284480
申请日：2011-10-28
CPC分类号： G11C7/18 , G11C7/12 , G11C29/846 , G11C2207/005
摘要： In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.
摘要翻译： 在可以并行访问的存储单元的阵列系统中降低功耗的电路中，本地评估电路连接到存储器单元阵列系统的存储单元和全局位线。 选择电路将全局位线分割成全局位线的上部和下部。 选择电路适于接收早期设定的预测信号，并且基于早期设定的预测信号将全局位线的上部连接到全局位线的下部。 早期设置的预测信号指示是否正在读取包括存储器单元的一组存储单元。 该电路还包括连接到全局位线的下部的N：1多路复用器，以接收全局位线的下部作为输入。
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