公开(公告)号：US06996174B2

公开(公告)日：2006-02-07

申请号：US10234545

申请日：2002-09-04

申请人： Francesco A. Campisano ,  Dennis P. Cheney ,  David A. Hrusecky ,  Chuck H. Ngai ,  Ronald S. Svec

发明人： Francesco A. Campisano ,  Dennis P. Cheney ,  David A. Hrusecky ,  Chuck H. Ngai ,  Ronald S. Svec

IPC分类号： H04N7/12

CPC分类号： H04N19/59 ,  H04N19/159 ,  H04N19/423 ,  H04N19/428 ,  H04N19/44 ,  H04N19/61

摘要： A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames. The full size I and P frames are used to support future decode operations, while the scaled I, P & B frames are retrieved for display.

公开(公告)号：US06542162B1

公开(公告)日：2003-04-01

申请号：US09094753

申请日：1998-06-15

申请人： David A. Hrusecky ,  Bryan J. Lloyd

发明人： David A. Hrusecky ,  Bryan J. Lloyd

IPC分类号： H04N5445

CPC分类号： H04N9/641 ,  G09G5/06 ,  G09G5/36 ,  G09G2340/125 ,  H04N21/434

摘要： An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

公开(公告)号：US06642934B2

公开(公告)日：2003-11-04

申请号：US10315322

申请日：2002-12-09

申请人： David A. Hrusecky ,  Bryan J. Lloyd

发明人： David A. Hrusecky ,  Bryan J. Lloyd

IPC分类号： H04N5445

CPC分类号： H04N9/641 ,  G09G5/06 ,  G09G5/36 ,  G09G2340/125 ,  H04N21/434

摘要： An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

摘要翻译： 提供了具有彩色映射模式，直接彩色模式和4：2：2配置文件模式的屏幕显示（OSD）处理器，处理方法和制造商品。 OSD处理器实现色彩映射OSD区域处理能力和直接颜色OSD区域处理能力，以及存储与OSD处理器耦合的视频解码器的4：2：2配置文件模式的量化器系数的能力。 OSD处理器的功能使用处理器内的公共嵌入式存储器来实现。 在颜色映射OSD区域处理期间，彩色表数据临时存储在嵌入式存储器中，而在直接颜色OSD区域处理中，直接颜色描述被存储在嵌入式存储器内。 当视频解码器对4：2：2格式化的图像进行解码时，OSD处理器的嵌入式存储器用于临时存储用于解码功能的反量化数据。

公开(公告)号：US5973740A

公开(公告)日：1999-10-26

申请号：US15463

申请日：1998-01-29

申请人： David A. Hrusecky

发明人： David A. Hrusecky

IPC分类号： G06T9/00 ,  H04N5/44 ,  H04N7/26 ,  H04N7/46 ,  H04N7/50 ,  H04N9/64 ,  H04N11/20

CPC分类号： H04N5/4401 ,  H04N19/186 ,  H04N19/423 ,  H04N19/427 ,  H04N19/428 ,  H04N19/433 ,  H04N19/577 ,  H04N19/59 ,  H04N19/61 ,  H04N19/80 ,  H04N21/4435 ,  H04N7/0122 ,  H04N9/64 ,  H04N11/20

摘要： A digital signal decoder system is provided for receiving digital video signals and processing them while reducing the external memory requirements for frame buffer storage for an MPEG-2 decoder through decimation. The system includes an expansion filter, such as a polyphase finite impulse response (FIR) horizontal filter for re-expanding decimated macroblock data to original form. This expansion filter is a variable filter which automatically adjusts expansion of the decimated macroblock data using the decimation factor employed by the decimation unit of the digital video decoding system. The automatically adjusting of expansion includes dividing the upsample ratio of the filter by the decimation factor received from the decimation unit. The expansion filter also includes a predefined phase correction associated with the decimation factor and style employed by the decimation unit. The predefined phase correction ensures spatial accuracy of macroblock data output from the expansion filter. The filter may alternatively comprise a high frequency filter for filtering high frequency affects from decimated macroblock data, e.g., when the digital video decoder system is sending decimated macroblock data to an associated display unit for display in decimated form.

摘要翻译： 提供数字信号解码器系统用于接收数字视频信号并进行处理，同时通过抽取减少MPEG-2解码器的帧缓冲存储器的外部存储器要求。 该系统包括扩展滤波器，例如用于将抽取的宏块数据重新扩展为原始形式的多相有限脉冲响应（FIR）水平滤波器。 该扩展滤波器是可变滤波器，其使用数字视频解码系统的抽取单元采用的抽取因子来自动调整抽取的宏块数据的扩展。 扩展的自动调整包括将滤波器的上采样比除以从抽取单元接收的抽取因子。 扩展滤波器还包括与抽取单元所采用的抽取因子和风格相关联的预定义相位校正。 预定义的相位校正确保从扩展滤波器输出的宏块数据的空间精度。 可替代地，滤波器可以包括高频滤波器，用于滤除来自抽取的宏块数据的高频影响，例如当数字视频解码器系统将抽取的宏块数据发送到相关联的显示单元以用抽取形式显示时。

公开(公告)号：US5375078A

公开(公告)日：1994-12-20

申请号：US991052

申请日：1992-12-15

申请人： David A. Hrusecky ,  Michael Putrino

发明人： David A. Hrusecky ,  Michael Putrino

IPC分类号： G06F7/544 ,  G06F7/38

CPC分类号： G06F7/5443 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49947

摘要： An arithmetic unit rapidly performs an XY+B floating point operation and yields a result equivalent to truncation of the product of X and Y before adding to B. Standard circuitry produces partial products from multiplier X and multiplicand Y, and a standard adder adds the partial products to yield a sum vector and a carry vector. Meanwhile, other circuitry predicts whether a most significant digit of a sum of the sum vector and the carry vector is zero or nonzero, based on less than all bits of the multiplier X and the multiplicand Y. If the most significant digit is certainly not equal to zero, a multiplexing circuit passes to a second adder a most significant N digits of the sum vector, a most significant N digits of the carry vector, a carry bit resulting from addition an (N-1)th most significant digit and lesser significant digits of the sum vector with an (N+1)th most significant digit and less significant digits of the carry vector, and an operand B. If the most significant digit is certainly equal to zero, then the multiplexing circuitry passes to the second adder a most significant N+1 digits of the sum vector, a most significant N+1 digits of the carry vector, a carry bit resulting from the addition of an (N+2)th most significant digit and less significant digits of the sum vector with an (N+2)th most significant digit and lesser significant digits of the carry vector, and the operand B.

摘要翻译： 算术单元快速执行XY + B浮点运算，并产生等于X和Y乘积截断的结果，然后再加上B。标准电路产生乘法器X和被乘数Y的部分乘积，标准加法器将部分 产生一个和矢量和一个进位向量。 同时，其他电路基于小于乘法器X和乘法器Y的所有比特来预测和矢量和进位向量之和的最高有效位是零还是非零。如果最高有效位肯定不相等 为零，多路复用电路将和向量的最高有效N位传送给第二加法器，进位向量的最高有效N位，由相加第（N-1）个最高有效数字和较小有效位产生的进位位 具有第（N + 1）个最高有效位和进位向量的低有效位的和矢量的位数以及操作数B.如果最高有效位肯定等于零，则多路复用电路传递到第二加法器 和矢量的最高有效N + 1个数字，进位向量的最高有效N + 1个数字，由相加和矢量的第（N + 2）个最高有效位和较低有效位相加而产生的进位位 最多（N + 2） 进位向量的有效数字和较低有效数字，以及操作数B.

公开(公告)号：US08422313B2

公开(公告)日：2013-04-16

申请号：US13284480

申请日：2011-10-28

申请人： Stefan Buettner ,  David A. Hrusecky ,  Werner Juchmes ,  Wolfgang Penth ,  Rolf Sautter

发明人： Stefan Buettner ,  David A. Hrusecky ,  Werner Juchmes ,  Wolfgang Penth ,  Rolf Sautter

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C29/846 ,  G11C2207/005

摘要： In a circuit that reduces power consumption in an array system of memory cells accessible in parallel, a local evaluation circuit is connected to a memory cell and a global bit line of the array system of memory cells. A selection circuitry splits the global bit line into an upper part and a lower part of the global bit line. The selection circuitry is adapted to receive an early set prediction signal and to connect the upper part of the global bit line to the lower part of the global bit line based on the early set prediction signal. The early set prediction signal indicates whether a set of memory cells, which include the memory cell, is being read. The circuit also includes a N:1 multiplexer connected to the lower part of the global bit line to receive the lower part of the global bit line as input.

摘要翻译： 在可以并行访问的存储单元的阵列系统中降低功耗的电路中，本地评估电路连接到存储器单元阵列系统的存储单元和全局位线。 选择电路将全局位线分割成全局位线的上部和下部。 选择电路适于接收早期设定的预测信号，并且基于早期设定的预测信号将全局位线的上部连接到全局位线的下部。 早期设置的预测信号指示是否正在读取包括存储器单元的一组存储单元。 该电路还包括连接到全局位线的下部的N：1多路复用器，以接收全局位线的下部作为输入。

公开(公告)号：US20100262781A1

公开(公告)日：2010-10-14

申请号：US12420118

申请日：2009-04-08

申请人： David A. Hrusecky ,  David S. Ray ,  Bruce J. Ronchetti ,  Shih-Hsiung S. Tung

发明人： David A. Hrusecky ,  David S. Ray ,  Bruce J. Ronchetti ,  Shih-Hsiung S. Tung

IPC分类号： G06F12/08

CPC分类号： G06F9/30043 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3857 ,  G06F12/0886

摘要： A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences.

摘要翻译： 访问数据高速缓存的加载指令可能是自然对齐，这导致高速缓存行交叉以完成访问。 说明性实施例提供了用于在多个高速缓存线之间加载数据的机制，而不需要在等待第二高速缓存行被访问的同时从第一高速缓存行部分数据存取的累加寄存器或收集点。 因为对分离的高速缓存行的访问在矢量重命名寄存器中连接，而不需要累加器，所以非对齐加载指令是完全可管理的并且可以刷新而没有清除后果。

公开(公告)号：US06898327B1

公开(公告)日：2005-05-24

申请号：US09535002

申请日：2000-03-23

申请人： David A. Hrusecky ,  Roger S. Rutter

发明人： David A. Hrusecky ,  Roger S. Rutter

IPC分类号： H04N5/21 ,  G06K9/40 ,  H04N5/445 ,  H04N7/26 ,  H04N19/00 ,  H04N21/422 ,  H04N21/431 ,  H04N21/47

CPC分类号： H04N7/0132 ,  H04N5/445

摘要： Flickering artifacts are removed from a displayed image by storing digital luminance values in a compressed form using disallowed luminance values clipped from a range of luminance values to encode run lengths of identical values of truncated luminance values and bits corresponding to bits truncated from the luminance values. A correction value is derived from a filter transfer function computed by summing an increase in correction value above a threshold within a range of luminance differences with a maximum change in correction value in each lower range, this providing a piecewise linear substantially quadratic transfer function without discontinuities that would engender other image artifacts. The non-linearity of the transfer function is this adaptive to different image conditions and types in regions of respective image planes and the correction factors implemented by the transfer function are freely adjustable to accommodate, for example, different scanning standards and display refresh rates.

摘要翻译： 通过使用从亮度值范围中剪切的不允许的亮度值，以压缩形式存储数字亮度值，以对与截断的亮度值相对应的位相对应的截取的亮度值和位的行编码的游程长度进行编码，从显示的图像中去除闪烁人造物。 通过将校正值的增加量超过亮度差的范围内的校正值的增加与每个下限范围内的校正值的最大变化相加得到的滤波器传递函数导出校正值，这提供了不间断的分段线性的基本上二次的传递函数 这将产生其他图像工件。 传递函数的非线性度是适应于各个图像平面区域中的不同图像条件和类型，并且由传递函数实现的校正因子可自由调节以适应例如不同的扫描标准和显示刷新率。

公开(公告)号：US06529244B1

公开(公告)日：2003-03-04

申请号：US09470277

申请日：1999-12-22

申请人： David A. Hrusecky

发明人： David A. Hrusecky

IPC分类号： H04N701

CPC分类号： H04N9/641 ,  H04N5/44504 ,  H04N21/42653 ,  H04N21/8146

摘要： An on-screen display processor for a digital video signal processing system is disclosed. The OSD processor includes logic for converting a graphics bitmap in 4:4:4 format to graphics image words in 4:2:2 format for blending with video image words in a blend multiplexer of the digital video decode system. The OSD processor provides the graphics image words with blended chrominance values each obtained by merging chrominance values of at least two adjacent picture elements of the graphics bitmap. The merging includes mathematically combining U chrominance values of the at least two adjacent picture elements to produce a blended U chrominance and mathematically combining the V chrominance values of the at least two picture elements to obtain a blended V chrominance. In one embodiment, the mathematically combining comprises averaging the U chrominance values to obtain the blended U chrominance and averaging the V chrominance values to obtain the blended V chrominance.

摘要翻译： 公开了一种用于数字视频信号处理系统的屏幕显示处理器。 OSD处理器包括用于将4：4：4格式的图形位图转换为4：2：2格式的图形图像字的逻辑，用于与数字视频解码系统的混合多路复用器中的视频图像字进行混合。 OSD处理器通过合并图形位图的至少两个相邻像素的色度值而获得的混合色度值提供图形图像字。 合并包括数学地组合至少两个相邻像素的U色度值以产生混合的U色度，并且数学地组合至少两个像素的V色度值以获得混合的V色度。 在一个实施例中，数学组合包括对U色度值进行平均以获得混合的U色度并平均V色度值以获得混合的V色度。

公开(公告)号：US06442206B1

公开(公告)日：2002-08-27

申请号：US09237600

申请日：1999-01-25

申请人： David A. Hrusecky

发明人： David A. Hrusecky

IPC分类号： H04B166

CPC分类号： H04N19/59

摘要： A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames. The full size I and P frames are used to support future decode operations, while the scaled I, P & B frames are retrieved for display. Anti-flicker logic is also included within the decode system for displaying scaled video in a flicker-free fashion.

摘要翻译： 提供数字视频解码器系统，方法和制品，其具有用于呈现全尺寸或预定缩小尺寸的视频的集成缩放能力，同时允许减少对帧缓冲存储器的外部存储器要求。 当系统处于缩放视频模式时，集成系统利用现有抽取单元来缩放解码的视频数据流。 显示模式开关逻辑监视正常视频模式和缩放视频模式之间的切换，其中切换发生在视频数据的解码流的显示的感知劣化。 缩放的解码视频帧被缓冲在帧缓冲器中，该帧缓冲器根据数字视频解码系统是处于正常视频模式还是缩放视频模式进行分区。 在缩放视频模式下，帧缓冲器适应全尺寸I和P帧以及缩放I，P＆B帧。 全尺寸I和P帧用于支持未来的解码操作，而缩放的I，P＆B帧被检索用于显示。 解码系统中还包括防闪烁逻辑，用于以无闪烁的方式显示缩放的视频。