摘要:
An apparatus and methods are provided for determining control parameters for image enhancement. In one embodiment a method for determining control parameters includes receiving image data for a first frame and calculating an adaptive threshold value based on the image data. The method includes determining a pixel slope distribution for a pixel window of the image data, wherein the pixel window is selected based on the adaptive threshold value and determining a spectrum estimation coefficient based on the pixel distribution, wherein the spectrum estimation coefficient is determined based on the spectral components of the image data. The method may then include determining one or more control parameters for enhancement of the image data based on the spectrum estimation coefficient, wherein the one or more control parameters relate to filtering parameters for adaptive enhancement of image data.
摘要:
An apparatus and methods are provided for determining control parameters for image enhancement. In one embodiment a method for determining control parameters includes receiving image data for a first frame and calculating an adaptive threshold value based on the image data. The method includes determining a pixel slope distribution for a pixel window of the image data, wherein the pixel window is selected based on the adaptive threshold value and determining a spectrum estimation coefficient based on the pixel distribution, wherein the spectrum estimation coefficient is determined based on the spectral components of the image data. The method may then include determining one or more control parameters for enhancement of the image data based on the spectrum estimation coefficient, wherein the one or more control parameters relate to filtering parameters for adaptive enhancement of image data.
摘要:
Multiple special purpose processing units are provided in a vector signal processor for concurrent, parallel processing, particularly of complex vectors. The principal processing units are an execution unit, a data movement unit, a control/register unit, a vector buffer unit, an instruction fetch unit, and a bus interface unit.
摘要:
An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for high computation throughput for digital signal processing (DSP) operations. The adder-subtracter and the adder have the same input operands, so that the sum and difference of these input operands can be computed simultaneously. A first and a second internal data bus are provided for transferring data and instructions within the arithmetic execution unit. The input/output operands and partial results are stored in a set of auxiliary registers. Most of these registers can be organized in pairs that for complex arithmetic computations are used to store the real and the imaginary parts of a complex operand. A register-pair can also simultaneously handle two different real operands. The operands are fetched from an internal data buffer from, for example, sources internal to the integrated circuit such as internal RAM, ROM and arithmetic registers. Computation results from the Multiplier, the Adder, and the Adder-Subtracter are temporary stored in the auxiliary registers before writing to the internal RAM or arithmetic registers of the integrated circuit. Data-flow in the vector arithmetic unit is controlled by a vector control unit.