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    Arithmetic unit in a vector signal processor using pipelined computational blocks
    2.
    发明授权
    Arithmetic unit in a vector signal processor using pipelined computational blocks 失效
    使用流水线计算块的矢量信号处理器中的算术单元

    公开(公告)号：US5053987A

    公开(公告)日：1991-10-01

    申请号：US430815

    申请日：1989-11-02

    申请人： Alexander Genusov ,  Ram B. Friedlander ,  Peter Feldman ,  Vlad Fruchter

    发明人： Alexander Genusov ,  Ram B. Friedlander ,  Peter Feldman ,  Vlad Fruchter

    IPC分类号： G06F7/48 ,  G06F7/50 ,  G06F7/52 ,  G06F7/57 ,  G06F15/78

    CPC分类号： G06F7/485 ,  G06F15/8076 ,  G06F7/4806 ,  G06F7/483 ,  G06F7/4876 ,  G06F2207/3884

    摘要： An arithmetic unit for a vector signal processor implements IEEE Standard 754 for Floating-Point Arithmetic. The arithmetic unit includes three pipelined floating-point computational blocks: a multiplier, an adder-subtracter, and an adder to provide for high computation throughput for digital signal processing (DSP) operations. The adder-subtracter and the adder have the same input operands, so that the sum and difference of these input operands can be computed simultaneously. A first and a second internal data bus are provided for transferring data and instructions within the arithmetic execution unit. The input/output operands and partial results are stored in a set of auxiliary registers. Most of these registers can be organized in pairs that for complex arithmetic computations are used to store the real and the imaginary parts of a complex operand. A register-pair can also simultaneously handle two different real operands. The operands are fetched from an internal data buffer from, for example, sources internal to the integrated circuit such as internal RAM, ROM and arithmetic registers. Computation results from the Multiplier, the Adder, and the Adder-Subtracter are temporary stored in the auxiliary registers before writing to the internal RAM or arithmetic registers of the integrated circuit. Data-flow in the vector arithmetic unit is controlled by a vector control unit.

    摘要翻译： 用于矢量信号处理器的算术单元实现用于浮点算术的IEEE标准754。 算术单元包括三个流水线浮点计算块：乘法器，加法器 - 减法器和加法器，用于为数字信号处理（DSP）操作提供高计算吞吐量。 加法器 - 减法器和加法器具有相同的输入操作数，使得可以同时计算这些输入操作数的和和差。 第一和第二内部数据总线被提供用于在算术执行单元内传送数据和指令。 输入/输出操作数和部分结果存储在一组辅助寄存器中。 大多数这些寄存器可以成对组织，用于复杂算术计算用于存储复数操作数的实部和虚部。 寄存器对也可以同时处理两个不同的实际操作数。 操作数从内部数据缓冲器中取出，例如内部RAM，ROM和算术寄存器等集成电路内部的源。 在写入集成电路的内部RAM或算术寄存器之前，乘法器，加法器和加法器 - 减法器的计算结果临时存储在辅助寄存器中。 矢量运算单元中的数据流由矢量控制单元控制。

    Bus arbitration and resource management for concurrent vector signal processor architecture
    3.
    发明授权
    Bus arbitration and resource management for concurrent vector signal processor architecture 失效
    并发矢量信号处理器架构的总线仲裁和资源管理

    公开(公告)号：US5263169A

    公开(公告)日：1993-11-16

    申请号：US784740

    申请日：1991-10-20

    申请人： Alexander Genusov ,  Ram B. Friedlander ,  Peter Feldman ,  Ricardo Jaliff

    发明人： Alexander Genusov ,  Ram B. Friedlander ,  Peter Feldman ,  Ricardo Jaliff

    IPC分类号： G06F9/38 ,  G06F13/364 ,  G06F15/347

    CPC分类号： G06F13/364 ,  G06F9/3836

    摘要： A concurrent vector signal processor includes a resource manager for utilization of captive signal processing resources. The first instructions in a temporary instruction queue are predecoded and the signal processing resources are selected to execute those first instructions.Arbitration system is provided for external buses connected to a concurrent vector signal processor. A processor arbiter supervises on a priority basis both captive processor resources and independent processor resources. A bus arbiter supervises on a priority basis external and internal buses.

    摘要翻译： 并行矢量信号处理器包括用于利用俘获信号处理资源的资源管理器。 临时指令队列中的第一条指令被预解码，并且选择信号处理资源来执行这些第一指令。 为与并发矢量信号处理器连接的外部总线提供仲裁系统。 处理器仲裁器以优先级为基础来监督强制处理器资源和独立的处理器资源。 总线仲裁员优先监督外部和内部公共汽车。