公开(公告)号：US3929512A

公开(公告)日：1975-12-30

申请号：US39591273

申请日：1973-09-10

Applicant: PHILIPS CORP

Inventor： NICHOLAS KEITH HARLOW ,  FORD RONALD ALFRED ,  BEALE JULIAN ROBERT ANTHONY

IPC: H01L21/00 ,  H01L29/8605

CPC classification number: H01L29/8605 ,  H01L21/00

Abstract: A method of improving the voltage linearity of a semiconductor resistor for use, for example, in integrated circuit manufacture, which linearity is deteriorated by the loss of carriers in the resistor at the vicinity of a junction separating the resistor region from the semiconductor body. The method consists of bombarding the semiconductor to implant therein in the vicinity of the junction neutral ions, such as neon, forming lattice damage. The concentration of implanted ions and lattice damage is so high as to reduce the effective mobility of charge carriers in the region resulting in the improved voltage linearity.

Abstract translation: 一种提高半导体电阻器的电压线性度的方法，例如在集成电路制造中，由于在电阻器区域与半导体本体分离的结的附近，电阻器中的载流子的损耗导致线性恶化。 该方法包括：轰击半导体以在接合中性离子（例如氖）附近植入其中，形成晶格损伤。 注入离子的浓度和晶格损伤是如此之高，以降低电荷载流子在该区域中的有效迁移率，导致改善的电压线性。

公开(公告)号：US3470076A

公开(公告)日：1969-09-30

申请号：US3470076D

申请日：1967-01-10

Applicant: PHILIPS CORP

Inventor： KLEIN THOMAS ,  NICHOLAS KEITH HARLOW

IPC: H01L21/3105 ,  H01L21/316 ,  B01K1/00

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/3105 ,  H01L21/31662