公开(公告)号：US3879613A

公开(公告)日：1975-04-22

申请号：US46824874

申请日：1974-05-09

Applicant: PHILIPS CORP

Inventor： SCOTT JULIAN PORTWAY ,  BEALE JULIAN ROBERT ANTHONY

IPC: H01J37/30 ,  H01J37/304 ,  H01L21/00 ,  H01J37/26

CPC classification number: H01J37/3045 ,  H01J37/30 ,  H01L21/00 ,  H01L2223/54453 ,  Y10S438/975

Abstract: A method of aligning a semiconductor body with respect to an electron beam pattern, comprising for each direction with respect to which alignment is desired, the steps of: forming on the semiconductor body a reference marker having two outer regions of one conductivity type semiconductor material separated by an intermediate region of opposite conductivity type semiconductor material; forming an alignment electron beam positionally fixed relative to the electron beam pattern and suitably crosssectioned such that when the electron beam pattern is aligned with respect to the semiconductor body, said alignment electron beam strikes said intermediate region midway between said two outer regions causing thereby equal currents diffusing thereto from each of said two outer regions; comparing the currents diffusing into said intermediate region from each of said two outer regions; and adjusting the relative position of the electron beam pattern with respect to the semiconductor body until said compared currents are equal.

Abstract translation: 相对于电子束图案对准半导体本体的方法，包括针对期望相对于哪个对准的每个方向的步骤：在半导体主体上形成具有两个外部区域的参考标记，所述两个外部区域分隔成一个导电型半导体材料 通过相反导电型半导体材料的中间区域; 形成相对于电子束图案位置固定的对准电子束，并适当地横截面，使得当电子束图案相对于半导体本体排列时，所述对准电子束在所述两个外部区域之间的中间部分处于所述两个外部区域之间的所述中间区域 从所述两个外部区域中的每一个向其扩散相等的电流; 比较从所述两个外部区域中的每一个扩散到所述中间区域的电流; 并且调整电子束图案相对于半导体本体的相对位置，直到所述比较电流相等。

公开(公告)号：US3704177A

公开(公告)日：1972-11-28

申请号：US3704177D

申请日：1970-12-15

Applicant: PHILIPS CORP

Inventor： BEALE JULIAN ROBERT ANTHONY

IPC: H01L21/00 ,  H01L21/331 ,  H01L27/00 ,  H01L29/00 ,  H01L29/10 ,  H01L7/54

CPC classification number: H01L29/1004 ,  H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/66295 ,  Y10S148/011 ,  Y10S148/106 ,  Y10S438/965

Abstract: A METHOD FOR MAKING A HIGH-FREQUENCY BIPOLAR TRANSISTOR IS DESCRIBED. THE METHOD EMPLOYS SELECTIVE ION IMPLANTATION TO FORM HIGHLY CONDUCTING MUTUALLY SPACED STRIPE PORTIONS IN THE BASE REGION OF THE TRANSISTOR. THE STRIPE PORTIONS MAY BE FORMED DIRECTLY BELOW AND SPACED FROM THE EMITTER REGION. A HEAVY METAL MASK DEFINED BY ELECTRON-RESIST METHODS MAY BE PROVIDED AT LEAST IN THE EMITTER WINDOW TO SELECTIVELY MASK AGAINST THE IMPLANTATION.

公开(公告)号：US3512055A

公开(公告)日：1970-05-12

申请号：US3512055D

申请日：1967-08-06

Applicant: PHILIPS CORP

Inventor： BEALE JULIAN ROBERT ANTHONY

IPC: H01L21/00 ,  H01L21/228 ,  H01L21/24 ,  H01L29/00 ,  H01L29/73 ,  H01L3/00

CPC classification number: H01L29/00 ,  H01L21/00 ,  H01L21/228 ,  H01L21/24 ,  H01L29/73

公开(公告)号：US3490847A

公开(公告)日：1970-01-20

申请号：US3490847D

申请日：1966-05-17

Applicant: PHILIPS CORP

Inventor： BERZ FEODORA ,  BEALE JULIAN ROBERT ANTHONY

IPC: G01N21/55 ,  G01J3/02

CPC classification number: G01N21/552

公开(公告)号：US3929512A

公开(公告)日：1975-12-30

申请号：US39591273

申请日：1973-09-10

Applicant: PHILIPS CORP

Inventor： NICHOLAS KEITH HARLOW ,  FORD RONALD ALFRED ,  BEALE JULIAN ROBERT ANTHONY

IPC: H01L21/00 ,  H01L29/8605

CPC classification number: H01L29/8605 ,  H01L21/00

Abstract: A method of improving the voltage linearity of a semiconductor resistor for use, for example, in integrated circuit manufacture, which linearity is deteriorated by the loss of carriers in the resistor at the vicinity of a junction separating the resistor region from the semiconductor body. The method consists of bombarding the semiconductor to implant therein in the vicinity of the junction neutral ions, such as neon, forming lattice damage. The concentration of implanted ions and lattice damage is so high as to reduce the effective mobility of charge carriers in the region resulting in the improved voltage linearity.

Abstract translation: 一种提高半导体电阻器的电压线性度的方法，例如在集成电路制造中，由于在电阻器区域与半导体本体分离的结的附近，电阻器中的载流子的损耗导致线性恶化。 该方法包括：轰击半导体以在接合中性离子（例如氖）附近植入其中，形成晶格损伤。 注入离子的浓度和晶格损伤是如此之高，以降低电荷载流子在该区域中的有效迁移率，导致改善的电压线性。

公开(公告)号：US3653978A

公开(公告)日：1972-04-04

申请号：US3653978D

申请日：1969-03-07

Applicant: PHILIPS CORP

Inventor： ROBINSON DAVID PHYTHIAN ,  BEALE JULIAN ROBERT ANTHONY ,  SHANNON JOHN MARTIN ,  KERR JOHN ANTHONY ,  DAS MUKUNDA BEHARI

IPC: H01L21/265 ,  H01L21/76 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/00 ,  H01L29/10 ,  H01L29/78 ,  H01L7/54

CPC classification number: H01L29/7838 ,  H01L21/26513 ,  H01L21/823807 ,  H01L27/0883 ,  H01L27/0925 ,  H01L29/00 ,  H01L29/1045 ,  Y10S148/053 ,  Y10S148/118 ,  Y10S148/145

Abstract: A method for making an IGFET is described. The method utilizes impurity ion implantation into the surface channel to determine the conductivity thereof. The advantages include special impurity profiles providing improved performance, better control over important parameters such as threshold voltage, the manufacture of improved tetrodes, and the manufacture of improved ICs using for example N- and P-channel devices, and depletion and enhancement devices combined in a single chip.

Abstract translation: 描述了制造IGFET的方法。 该方法利用杂质离子注入表面通道来确定其电导率。 这些优点包括提供改进性能的特殊杂质分布，更好地控制诸如阈值电压，改进的四极杆的制造以及使用例如N和P沟道器件的改进的IC的制造，以及组合的耗尽和增强器件 单芯片

公开(公告)号：US3449648A

公开(公告)日：1969-06-10

申请号：US3449648D

申请日：1967-02-20

Applicant: PHILIPS CORP

Inventor： BEALE JULIAN ROBERT ANTHONY ,  BEER ANDREW FRANCIS

IPC: H01L23/29 ,  H01L23/482 ,  H01L29/00 ,  H01L11/14

CPC classification number: H01L23/291 ,  H01L23/4824 ,  H01L29/00 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00