公开(公告)号：US20100214026A1

公开(公告)日：2010-08-26

申请号：US12682352

申请日：2008-10-10

申请人： Padmanava Sen ,  Saikat Sarkar ,  Stephane Pinel ,  Joy Laskar ,  Francesco Barale

发明人： Padmanava Sen ,  Saikat Sarkar ,  Stephane Pinel ,  Joy Laskar ,  Francesco Barale

IPC分类号： H03L7/099

CPC分类号： H03K23/483 ,  H03B5/1852 ,  H03B21/02 ,  H03J3/185 ,  H03L7/099 ,  H03L7/193 ,  H03L7/24

摘要： A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

摘要翻译： 压控振荡器锁相环（VCO-PLL）系统包括实施四通道架构的压控振荡器（VCO）系统，使得两个频带支持两个通道; 锁相环（PLL）系统; 和搅拌机系统。 VCO系统还包括控制电路; 适于接收源电压的第一交叉耦合振荡器系统; 适于接收源电压的第二交叉耦合振荡器系统; 以及适于保护第一和第二交叉耦合振荡器系统的多个隔离缓冲器系统。

公开(公告)号：US08067987B2

公开(公告)日：2011-11-29

申请号：US12682352

申请日：2008-10-10

申请人： Padmanava Sen ,  Saikat Sarkar ,  Stephane Pinel ,  Joy Laskar ,  Francesco Barale

发明人： Padmanava Sen ,  Saikat Sarkar ,  Stephane Pinel ,  Joy Laskar ,  Francesco Barale

IPC分类号： H03L7/00

CPC分类号： H03K23/483 ,  H03B5/1852 ,  H03B21/02 ,  H03J3/185 ,  H03L7/099 ,  H03L7/193 ,  H03L7/24

摘要： A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

摘要翻译： 压控振荡器锁相环（VCO-PLL）系统包括实施四通道架构的压控振荡器（VCO）系统，使得两个频带支持两个通道; 锁相环（PLL）系统; 和搅拌机系统。 VCO系统还包括控制电路; 适于接收源电压的第一交叉耦合振荡器系统; 适于接收源电压的第二交叉耦合振荡器系统; 以及适于保护第一和第二交叉耦合振荡器系统的多个隔离缓冲器系统。

公开(公告)号：US07489201B2

公开(公告)日：2009-02-10

申请号：US11801363

申请日：2007-05-09

申请人： Saikat Sarkar ,  Padmanava Sen ,  Stephane Pinel ,  Joy Laskar

发明人： Saikat Sarkar ,  Padmanava Sen ,  Stephane Pinel ,  Joy Laskar

IPC分类号： H03F3/04

CPC分类号： H03F1/22 ,  H03F3/191 ,  H03F3/60 ,  H03F2200/181 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387

摘要： Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 μm SiGe process (FT=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable FT. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 μm SiGe process.

摘要翻译： 公开了一种用于毫米波共源共栅放大器的增益技术。 可以使用0.18μmSiGe工艺（FT = 140GHz）来实现示例性技术。 还已经表明，该技术对于具有相当的FT的CMOS工艺是有效的。 测量一个示例性的增益增益共源共栅级，具有高于9 dB的增益，1 GHz带宽高于6 GHz，直流功耗为13 mW。 另外，没有增益升压的一个级联级可以与两个增益升压的共源共栅放大器级级联以实现三级LNA。 测量的稳定增益在60 GHz时高于24 dB，对于25 mW的直流功耗，3.1 GHz的3 dB带宽。 相信这是使用0.18 mum SiGe工艺的第一个60 GHz LNA，具有高于20 dB的增益。

公开(公告)号：US20070273445A1

公开(公告)日：2007-11-29

申请号：US11801363

申请日：2007-05-09

申请人： Saikat Sarkar ,  Padmanava Sen ,  Stephane Pinel ,  Joy Laskar

发明人： Saikat Sarkar ,  Padmanava Sen ,  Stephane Pinel ,  Joy Laskar

IPC分类号： H03G3/00

CPC分类号： H03F1/22 ,  H03F3/191 ,  H03F3/60 ,  H03F2200/181 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387

摘要： Disclosed is a gain boosting technique for use with millimeter-wave cascode amplifiers. The exemplary technique may be implemented using a 0.18 μm SiGe process (FT=140 GHz). It has also been shown that the technique is effective for CMOS processes with comparable FT. An exemplary gain-enhanced cascode stage was measured to have higher than 9 dB gain with a 1-dB bandwidth above 6 GHz with a DC power consumption of 13 mW. In addition, one cascode stage without gain boosting may be cascaded with two gain-boosted cascode amplifier stages to implement a three-stage LNA. The measured stable gain is higher than 24 dB at 60 GHz with a 3-dB bandwidth of 3.1 GHz for 25 mW of DC power consumption. It is believed that this is the first 60 GHz LNA with a higher than 20 dB gain using a 0.18 μm SiGe process.

摘要翻译： 公开了一种用于毫米波共源共栅放大器的增益技术。 可以使用0.18μmSiGe工艺（F> T = 140GHz）来实现示例性技术。 还已经表明，该技术对于具有相当的F T T T的CMOS工艺是有效的。 测量一个示例性的增益增益共源共栅级，具有高于9 dB的增益，1 GHz带宽高于6 GHz，直流功耗为13 mW。 另外，没有增益升压的一个级联级可以与两个增益升压的共源共栅放大器级级联以实现三级LNA。 测量的稳定增益在60 GHz时高于24 dB，对于25 mW的直流功耗，3.1 GHz的3 dB带宽。 相信这是使用0.18 mum SiGe工艺的第一个60 GHz LNA，具有高于20 dB的增益。

公开(公告)号：US08686771B2

公开(公告)日：2014-04-01

申请号：US13485413

申请日：2012-05-31

申请人： Emmanouil Frantzeskakis ,  Ioannis L. Syllaios ,  Georgios Sfikas ,  Henrik Jensen ,  Stephen Wu ,  Padmanava Sen

发明人： Emmanouil Frantzeskakis ,  Ioannis L. Syllaios ,  Georgios Sfikas ,  Henrik Jensen ,  Stephen Wu ,  Padmanava Sen

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/1976 ,  H03L2207/50

摘要： The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.

摘要翻译： 本公开涉及用于建立和维持所生成的输出信号和参考输入信号之间的相位关系的数字锁相环（DPLL）和混合锁相环（HPLL）。 DPLL使用基于计数器的循环来初始将DPLL锁定。 此后，DPLL禁用基于计数器的循环并切换到具有多模式分频器（MMD）的回路。 DPLL可以实现消除技术，以减少由MMD引入的相位噪声。 HPLL还包括一个带有MMD的循环。 HPLL可以实现类似的消除技术，以减少由MMD引入的相位噪声。