公开(公告)号：US6057200A

公开(公告)日：2000-05-02

申请号：US831360

申请日：1997-04-01

申请人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

发明人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/43

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L29/0847 ,  Y10S438/969

摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

摘要翻译： 一种形成相对于单晶硅衬底的场效晶体管的方法，其中晶体管具有升高的源极和升高的漏极，包括：a）在单晶硅衬底上提供晶体管栅极，栅极被封装在电绝缘材料中; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内部，并且在清洁步骤之后，在与晶体管栅极相邻的清洁的衬底表面上化学气相沉积导电掺杂的非多晶硅层，非多晶硅层具有外表面，衬底 不会在清洗时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，和ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。 还要求一种场效应晶体管。

公开(公告)号：US5759905A

公开(公告)日：1998-06-02

申请号：US956918

申请日：1997-10-23

申请人： Pai-Hung Pan ,  Sujit Sharan ,  Kirk Prall

发明人： Pai-Hung Pan ,  Sujit Sharan ,  Kirk Prall

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76877

摘要： A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 ; e) after increasing the dopant concentration of the first layer, providing a second layer of semiconductive material over the first layer and to within the first remaining opening, the second layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; f) after providing the second layer within the first remaining opening, increasing the average conductivity enhancing dopant concentration of the second layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 ; and g) providing the contact opening to be substantially filled with semiconductive material having an average conductivity enhancing dopant concentration of greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 to define a conductively doped semiconductive material plug within the contact opening.

公开(公告)号：US5677573A

公开(公告)日：1997-10-14

申请号：US743502

申请日：1996-11-04

申请人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

发明人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/43

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L29/0847 ,  Y10S438/969

摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

摘要翻译： 一种形成相对于单晶硅衬底的场效晶体管的方法，其中晶体管具有升高的源极和升高的漏极，包括：a）在单晶硅衬底上提供晶体管栅极，栅极被封装在电绝缘材料中; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外部暴露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内部，并且在清洁步骤之后，在与晶体管栅极相邻的清洁的衬底表面上化学气相沉积导电掺杂的非多晶硅层，非多晶硅层具有外表面，衬底 不会在清洗时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，以及ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。 还要求一种场效应晶体管。

公开(公告)号：US6067680A

公开(公告)日：2000-05-30

申请号：US70127

申请日：1998-04-29

申请人： Pai-Hung Pan ,  Sujit Sharan ,  Kirk Prall

发明人： Pai-Hung Pan ,  Sujit Sharan ,  Kirk Prall

IPC分类号： H01L21/768 ,  H01L21/22

CPC分类号： H01L21/76877

摘要： A semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening includes, a) providing a node location and a plug molding layer outwardly thereof; b) providing a contact opening through the plug molding layer to the node location; c) providing a first layer of semiconductive material over the molding layer to within the contact opening, the first layer thickness being less than one-half the contact opening width to leave a first remaining opening, the first layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; d) after providing the first layer, increasing the average conductivity enhancing dopant concentration of the first layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 ; e) after increasing the dopant concentration of the first layer, providing a second layer of semiconductive material over the first layer and to within the first remaining opening, the second layer having an average conductivity enhancing dopant concentration from 0 atoms/cm.sup.3 to about 5.times.10.sup.18 atoms/cm.sup.3 ; f) after providing the second layer within the first remaining opening, increasing the average conductivity enhancing dopant concentration of the second layer to greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 ; and g) providing the contact opening to be substantially filled with semiconductive material having an average conductivity enhancing dopant concentration of greater than or equal to about 1.times.10.sup.19 atoms/cm.sup.3 to define a conductively doped semiconductive material plug within the contact opening.

摘要翻译： 在接触开口内形成导电掺杂半导体材料塞的半导体加工方法包括：a）向外提供节点位置和插塞模制层; b）通过插塞成型层提供到节点位置的接触开口; c）在模制层上提供第一层半导体材料到接触开口内，第一层厚度小于接触开口宽度的一半以留下第一剩余开口，第一层具有平均导电性增强掺杂剂浓度 从0原子/ cm3至约5×1018原子/ cm3; d）在提供第一层之后，将第一层的平均导电率增加掺杂剂浓度增加到大于或等于约1×1019原子/ cm3; e）在增加第一层的掺杂剂浓度之后，在第一层上提供第二层半导体材料，并且在第一剩余开口内，第二层具有从0原子/厘米3至约5×10 18原子的平均导电率增强掺杂剂浓度 / cm3; f）在第一剩余开口中提供第二层之后，将第二层的平均导电性增强掺杂剂浓度增加到大于或等于约1×1019原子/ cm3; 并且g）使所述接触开口基本上填充有具有大于或等于约1×1019原子/ cm3的平均导电性增强掺杂剂浓度的半导体材料，以在所述接触开口内限定导电掺杂的半导体材料塞。

公开(公告)号：US5831334A

公开(公告)日：1998-11-03

申请号：US912899

申请日：1997-08-15

申请人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

发明人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/43

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L29/0847 ,  Y10S438/969

摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

摘要翻译： 一种形成相对于单晶硅衬底的场效晶体管的方法，其中晶体管具有升高的源极和升高的漏极，包括：a）在单晶硅衬底上提供晶体管栅极，栅极被封装在电绝缘材料中; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内部，并且在清洁步骤之后，在与晶体管栅极相邻的清洁的衬底表面上化学气相沉积导电掺杂的非多晶硅层，非多晶硅层具有外表面，衬底 不会在清洗时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，以及ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。 还要求一种场效应晶体管。

公开(公告)号：US5637518A

公开(公告)日：1997-06-10

申请号：US543705

申请日：1995-10-16

申请人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

发明人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/43 ,  H01L21/8234

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L29/0847 ,  Y10S438/969

摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated in electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing a conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

摘要翻译： 一种形成相对于单晶硅衬底的场效晶体管的方法，其中晶体管具有升高的源极和升高的漏极，包括：a）在单晶硅衬底上提供晶体管栅极，栅极被封装在电绝缘材料中; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内部，并且在清洁步骤之后，在与晶体管栅极相邻的清洁的衬底表面上化学气相沉积导电掺杂的非多晶硅层，非多晶硅层具有外表面，衬底 不会在清洗时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，和ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。 还要求一种场效应晶体管。

公开(公告)号：US5998844A

公开(公告)日：1999-12-07

申请号：US153088

申请日：1998-09-14

申请人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

发明人： Kirk Prall ,  Pai-Hung Pan ,  Sujit Sharan

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L29/08 ,  H01L29/43

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L29/0847 ,  Y10S438/969

摘要： A method of forming a field effect transistor relative to a monocrystalline silicon substrate, where the transistor has an elevated source and an elevated drain, includes: a) providing a transistor gate over the monocrystalline silicon substrate, the gate being encapsulated fin electrically insulative material; b) providing outer exposed monocrystalline silicon substrate surfaces adjacent the transistor gate; c) cleaning the outer exposed substrate surfaces to remove oxide and impurities therefrom; d) within a rapid thermal chemical vapor deposition reactor and after the cleaning step, chemical vapor depositing conductively doped non-polycrystalline silicon layer over the cleaned substrate surfaces adjacent the transistor gate, the non-polycrystalline silicon layer having an outer surface, the substrate not being exposed to oxidizing or contaminating conditions between the time of cleaning and the chemical vapor depositing; and e) after chemical vapor depositing, exposing the doped non-polycrystalline silicon layer to high temperature annealing conditions effective to, i) produce doped monocrystalline silicon extending outwardly from the substrate surface, and ii) produce doped polycrystalline silicon extending inwardly from the outer surface; the doped monocrystalline silicon and doped polycrystalline silicon joining at an interface which is displaced elevationally outward of the substrate surfaces. A field effect transistor is also claimed.

摘要翻译： 一种形成场效应晶体管相对于单晶硅衬底的方法，其中晶体管具有升高的源极和升高的漏极，其包括：a）在单晶硅衬底上提供晶体管栅极，栅极是封装的鳍状电绝缘材料; b）提供与晶体管栅极相邻的外部暴露的单晶硅衬底表面; c）清洁外露的基底表面以从其中除去氧化物和杂质; d）在快速热化学气相沉积反应器内，并且在清洁步骤之后，化学气相沉积导电掺杂的非多晶硅层在与晶体管栅极相邻的清洁的衬底表面上，非多晶硅层具有外表面，衬底不 在清洁时间和化学气相沉积之间暴露于氧化或污染条件; 以及e）在化学气相沉积之后，将所述掺杂的非多晶硅层暴露于高温退火条件，所述高温退火条件有效地，i）产生从所述衬底表面向外延伸的掺杂单晶硅，和ii）产生从所述外表面向内延伸的掺杂多晶硅 ; 掺杂的单晶硅和掺杂的多晶硅在衬底表面的高度位移的界面处接合。 还要求一种场效应晶体管。

公开(公告)号：US06255209B1

公开(公告)日：2001-07-03

申请号：US09376023

申请日：1999-08-19

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： Methods are provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). The methods include forming titanium in the contact. One method includes forming titanium by combining a titanium precursor in the presence of hydrogen, H2. Another method includes forming titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. A further method includes forming titanium by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen.

摘要翻译： 提供了通过化学气相沉积（CVD）在集成电路中形成接触的方法。 所述方法包括在接触中形成钛。 一种方法包括通过在氢气存在下将钛前体组合而形成钛。 另一种方法包括在氢的存在下将四氯化钛，TiCl 4组合形成钛。 另一种方法包括在氢的存在下，通过组合四（二甲基氨基）钛，Ti（N（CH 3）2）4形成钛。

公开(公告)号：US06208033B1

公开(公告)日：2001-03-27

申请号：US09377253

申请日：1999-08-19

申请人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

发明人： Trung T. Doan ,  Gurtej Singh Sandhu ,  Kirk Prall ,  Sujit Sharan

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  C23C16/02 ,  C23C16/0236 ,  C23C16/42 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76855

摘要： Apparatus having titanium silicide and titanium formed by chemical vapor deposition (CVD) in a contact. The chemical vapor deposition includes forming titanium silicide and/or titanium by combining a titanium precursor in the presence of hydrogen, H2. The chemical vapor deposition may further include forming titanium silicide and/or titanium by combining titanium tetrachloride, TiCl4, in the presence of hydrogen. The chemical vapor deposition may further include forming titanium silicide and/or by combining tetradimethyl amino titanium, Ti(N(CH3)2)4, in the presence of hydrogen. For production of titanium silicide, reaction of the titanium precursor may occur with a silicon precursor or a silicon source occurring as part of the contact. Use of a silicon precursor reduces depletion of a silicon base layer in the contact.

摘要翻译： 具有通过化学气相沉积（CVD）在接触中形成的钛硅化物和钛的装置。 化学气相沉积包括通过在氢气存在下将钛前体组合而形成钛硅化物和/或钛。 化学气相沉积还可以包括在氢的存在下通过组合四氯化钛TiCl 4来形成硅化钛和/或钛。 化学气相沉积可以进一步包括在氢的存在下形成硅化钛和/或通过组合四（二甲基氨基）钛（N（CH 3）2）4）。 对于硅化钛的生产，钛前体的反应可以与作为接触部分的硅前体或硅源发生。 硅前体的使用减少了接触中硅基层的耗尽。

公开(公告)号：US06812512B2

公开(公告)日：2004-11-02

申请号：US09832272

申请日：2001-04-10

申请人： Kirk Prall ,  Howard E. Rhodes ,  Sujit Sharan ,  Gurtel Sandhu ,  Philip J. Ireland

发明人： Kirk Prall ,  Howard E. Rhodes ,  Sujit Sharan ,  Gurtel Sandhu ,  Philip J. Ireland

IPC分类号： H01L27108

CPC分类号： H01L21/76897 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/7687 ,  Y10S257/915

摘要： This invention is a process for manufacturing a random access memory array. Each memory cell within the array which results from the process incorporates a stacked capacitor, a silicon nitride coated access transistor gate electrode, and a self-aligned high-aspect-ratio digit line contact having a tungsten plug which extends from the substrate to a metal interconnect structure located at a level above the stacked capacitor. The contact opening is lined with titanium metal which is in contact with the substrate, and with titanium nitride that is in contact with the plug. Both the titanium metal and the titanium nitride are deposited via chemical vapor deposition reactions.

摘要翻译： 本发明是用于制造随机存取存储器阵列的方法。 由该工艺产生的阵列内的每个存储单元都包含堆叠电容器，氮化硅涂层存取晶体管栅极电极以及具有从基板延伸到金属的钨插头的自对准高纵横比数字线接触件 位于层叠电容器上方的互连结构。 接触开口衬有与基底接触的钛金属和与插塞接触的氮化钛。 通过化学气相沉积反应沉积钛金属和氮化钛。