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公开(公告)号：US09653510B2
公开(公告)日：2017-05-16
申请号：US14554450
申请日：2014-11-26
Inventor： Tokuhiko Tamaki , Hirohisa Ohtsuki , Ryohei Miyagawa , Motonori Ishii
IPC: H01L27/146 , H04N5/3745
CPC classification number: H01L27/14603 , H01L27/14609 , H01L27/14612 , H01L27/14636 , H01L27/14643 , H04N5/3698 , H04N5/3745
Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.
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公开(公告)号：US09386248B2
公开(公告)日：2016-07-05
申请号：US14554037
申请日：2014-11-25
Inventor： Hirohisa Ohtsuki , Akira Tanaka , Ryohei Miyagawa
IPC: H04N5/374 , H01L27/146 , H04N5/3745
CPC classification number: H04N5/3741 , H01L27/14603 , H01L27/14636 , H01L27/14638 , H01L27/1464 , H01L27/14643 , H01L27/14665 , H04N5/37457
Abstract: A pixel includes: a photoelectric conversion unit that photoelectrically converts incident light and has an upper electrode, a lower electrode, and a photoelectric conversion film interposed between the upper electrode and the lower electrode; an amplifying transistor that outputs a signal according to an amount of a signal charge generated in the photoelectric conversion unit; a charge transfer line that connects the lower electrode and the amplifying transistor; and an output line that outputs the signal from the amplifying transistor, wherein at least a part of the output line is disposed to overlap the lower electrode without another line interposed therebetween.
Abstract translation: 像素包括：光电转换单元，其对入射光进行光电转换，并具有插入在上电极和下电极之间的上电极，下电极和光电转换膜; 放大晶体管，其根据在所述光电转换单元中产生的信号电荷的量输出信号; 连接下电极和放大晶体管的电荷传输线; 以及输出线，其输出来自所述放大晶体管的信号，其中所述输出线的至少一部分设置成与所述下电极重叠，而不插入另一条线。
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公开(公告)号：US20210005650A1
公开(公告)日：2021-01-07
申请号：US17025620
申请日：2020-09-18
Inventor： Tokuhiko TAMAKI , Hirohisa Ohtsuki , Ryohei Miyagawa , Motonori Ishii
IPC: H01L27/146 , H04N5/3745
Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.
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公开(公告)号：US10600826B2
公开(公告)日：2020-03-24
申请号：US15806139
申请日：2017-11-07
Inventor： Hirohisa Ohtsuki
IPC: H04N5/3745 , H01L27/146
Abstract: A pixel array in a solid-state imaging device includes first and second signal lines provided for each column. A pixel belongs to a first or second group on a row-by-row basis and includes a photoelectric conversion film, a FD line for accumulating signal charge, and an amplifier transistor for providing a voltage according to the signal charge. The pixel in the first group further includes a selection transistor for proving output voltage of the amplifier transistor to the first signal line, and the pixel in the second group further includes a selection transistor for proving output voltage of the amplifier transistor to the second signal line. The first signal line is disposed between the FD line in the first group and the second signal line, and the second signal line is disposed between the FD line in the second group and the first signal line.
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公开(公告)号：US10103181B2
公开(公告)日：2018-10-16
申请号：US15487941
申请日：2017-04-14
Inventor： Tokuhiko Tamaki , Hirohisa Ohtsuki , Ryohei Miyagawa , Motonori Ishii
IPC: H01L27/146 , H04N5/369 , H04N5/3745
Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.
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Patent Agency Ranking
公开(公告)号：US09825072B2
公开(公告)日：2017-11-21
申请号：US14553586
申请日：2014-11-25
Inventor： Hirohisa Ohtsuki
IPC: H01L27/00 , H01L27/146 , H04N5/3745
CPC classification number: H01L27/14603 , H01L27/14643 , H04N5/3745
Abstract: A pixel array in a solid-state imaging device includes first and second signal lines provided for each column. A pixel belongs to a first or second group on a row-by-row basis and includes a photoelectric conversion film, a FD line for accumulating signal charge, and an amplifier transistor for providing a voltage according to the signal charge. The pixel in the first group further includes a selection transistor for proving output voltage of the amplifier transistor to the first signal line, and the pixel in the second group further includes a selection transistor for proving output voltage of the amplifier transistor to the second signal line. The first signal line is disposed between the FD line in the first group and the second signal line, and the second signal line is disposed between the FD line in the second group and the first signal line.
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公开(公告)号：US12080728B2
公开(公告)日：2024-09-03
申请号：US17969411
申请日：2022-10-19
Inventor： Hirohisa Ohtsuki
IPC: H01L27/146 , H04N25/77
CPC classification number: H01L27/14603 , H01L27/14643 , H04N25/77
Abstract: An imaging device incudes a pixel array including pixels arranged in columns and rows, one of the columns including a first pixel in a first row and a second pixel in a second row; a first signal line, to which the first pixel is coupled, and a second signal line, to which the second pixel is coupled, extending in a column direction of the pixels; and a first shield line, to which the first pixel is coupled, extending in the column direction. The first signal line, the first shield line, and the second signal line are arranged along a row direction of the pixels in that order.
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公开(公告)号：US11605656B2
公开(公告)日：2023-03-14
申请号：US17025620
申请日：2020-09-18
Inventor： Tokuhiko Tamaki , Hirohisa Ohtsuki , Ryohei Miyagawa , Motonori Ishii
IPC: H01L27/146 , H04N5/3745 , H04N5/369
Abstract: A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.
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公开(公告)号：US11508764B2
公开(公告)日：2022-11-22
申请号：US16803758
申请日：2020-02-27
Inventor： Hirohisa Ohtsuki
IPC: H01L27/146 , H04N5/3745
Abstract: An imaging device incudes a pixel array including pixels arranged in columns and rows, one of the columns including a first pixel in a first row and a second pixel in a second row; a first signal line, to which the first pixel is coupled, and a second signal line, to which the second pixel is coupled, extending in a column direction of the pixels; and a first shield line, to which the first pixel is coupled, extending in the column direction. The first signal line, the first shield line, and the second signal line are arranged along a row direction of the pixels in that order.
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公开(公告)号：US09942506B2
公开(公告)日：2018-04-10
申请号：US15720668
申请日：2017-09-29
Inventor： Mitsuyoshi Mori , Hirohisa Ohtsuki , Yoshiyuki Ohmori , Yoshihiro Sato , Ryohei Miyagawa
IPC: H04N5/378 , H01L27/146 , H04N5/3745
CPC classification number: H04N5/378 , H01L27/14603 , H01L27/1461 , H01L27/1464 , H01L27/14645 , H04N5/3745
Abstract: A solid-state imaging device according to the present disclosure includes pixels arranged two-dimensionally, each of the pixels including: a metal electrode; a photoelectric conversion layer that is on the metal electrode and converts light into an electrical signal; a transparent electrode on the photoelectric conversion layer; an electric charge accumulation region that is electrically connected to the metal electrode and accumulates electric charges from the photoelectric conversion layer; an amplifier transistor that applies a signal voltage according to an amount of the electric charges in the electric charge accumulation region; and a reset transistor that resets electrical potential of the electric charge accumulation region, in which the reset transistor includes a gate oxide film thicker than a gate oxide film of the amplifier transistor.
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