公开(公告)号：US20160064376A1

公开(公告)日：2016-03-03

申请号：US14938803

申请日：2015-11-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： HIROYUKI HANDA ,  HIDEKAZU UMEDA ,  SATOSHI TAMURA ,  TETSUZO UEDA

IPC: H01L27/06 ,  H01L29/861 ,  H01L23/535 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L27/0629 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0635 ,  H01L27/095 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.

Abstract translation: 一种半导体装置，包括：基板; 形成在所述基板上的氮化物半导体层; 形成在所述氮化物半导体层上的晶体管，并且包括依次设置的源电极，栅极电极和漏极电极; 以及形成在氮化物半导体层上的二极管，并且包括依次设置的阳极电极和阴极电极。 半导体装置具有晶体管/二极管对，其中源电极，栅电极，漏电极，阳极电极和阴极电极依次依次设置，晶体管的漏电极和阳极电极 二极管通过漏极/阳极公共电极布线连接并用作公共电极。

公开(公告)号：US20160056245A1

公开(公告)日：2016-02-25

申请号：US14930628

申请日：2015-11-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： YUSUKE KINOSHITA ,  SATOSHI TAMURA ,  TETSUZO UEDA

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/205 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/66916 ,  H01L29/66924 ,  H01L29/7786 ,  H01L29/8086

Abstract: A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0≦p+q≦1, 0≦p, and 0≦q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0≦r+s≦1, 0≦r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0≦t+u≦1, 0≦t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0≦x+y≦1, 0≦y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.

Abstract translation: 半导体器件包括：由InpAlqGa1-p-qN（0＆nlE; p + q＆nlE; 1,0＆amp; nlE; p和0＆nlE; q）制成的沟道层; 阻挡层，其形成在沟道层上，并且由InrAlsGa1-r-sN（0＆lt; nlE; r + s＆nlE; 1,0＆amp; nlE; r）制成，其带隙大于沟道层的带隙; 扩散抑制层，其被选择性地形成在阻挡层上并由IntAluGa1-t-uN（0＆lt; nlE; t + u＆nlE; 1,0＆amp; nlE; t和s> u）制成; p型导电层，其形成在扩散抑制层上，由具有p型导电性的In x Al y Ga 1-x-y N（0＆lt; n 1; x + y＆nlE; 1,0＆amp; 以及形成在p型导电层上的栅电极。

公开(公告)号：US20150179741A1

公开(公告)日：2015-06-25

申请号：US14636149

申请日：2015-03-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： HIDEKAZU UMEDA ,  KAZUHIRO KAIBARA ,  SATOSHI TAMURA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L29/06 ,  H01L29/0661 ,  H01L29/10 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7786

Abstract: A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 μm-thick undoped GaN layer, and 20 nm-thick undoped AlGaN having an Al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped AlGaN layer. Further, in the undoped GaN layer and the undoped AlGaN layer immediately below a gate wire, a high resistance region, the resistance of which is increased by for example, ion implantation with Ar or the like, is formed, and a boundary between the high resistance region and an element region is positioned immediately below the gate wire.

Abstract translation: 氮化物半导体器件中的寄生电容和漏电流减小。 例如，将AlN，2μm厚的未掺杂的GaN层和Al组成比为20％的20nm厚的未掺杂的AlGaN构成的100nm厚的缓冲层依次外延生长在例如 由硅制成的衬底以及源电极和漏电极形成为与未掺杂的AlGaN层欧姆接触。 此外，在栅极布线正下方的未掺杂的GaN层和未掺杂的AlGaN层中，形成高电阻区域，其电阻例如通过Ar等的离子注入而增加，并且高电阻区域 电阻区域和元件区域位于栅极线的正下方。