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公开(公告)号:US20160064376A1
公开(公告)日:2016-03-03
申请号:US14938803
申请日:2015-11-11
Inventor: HIROYUKI HANDA , HIDEKAZU UMEDA , SATOSHI TAMURA , TETSUZO UEDA
IPC: H01L27/06 , H01L29/861 , H01L23/535 , H01L29/778 , H01L29/20 , H01L29/417
CPC classification number: H01L27/0629 , H01L23/535 , H01L27/0605 , H01L27/0635 , H01L27/095 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/417 , H01L29/41758 , H01L29/41766 , H01L29/7786 , H01L29/7787 , H01L29/861 , H01L29/872 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor apparatus includes a substrate; a nitride semiconductor layer formed on the substrate; a transistor formed on the nitride semiconductor layer, and including a source electrode, a gate electrode, and a drain electrode disposed in this order; and a diode formed on the nitride semiconductor layer, and including an anode electrode and a cathode electrode disposed in this order. The semiconductor apparatus has a transistor/diode pair in which the source electrode, the gate electrode, the drain electrode, the anode electrode, and the cathode electrode are sequentially disposed in this order, and the drain electrode of the transistor and the anode electrode of the diode are connected by a drain/anode common electrode wiring and serve as a common electrode.
Abstract translation: 一种半导体装置,包括:基板; 形成在所述基板上的氮化物半导体层; 形成在所述氮化物半导体层上的晶体管,并且包括依次设置的源电极,栅极电极和漏极电极; 以及形成在氮化物半导体层上的二极管,并且包括依次设置的阳极电极和阴极电极。 半导体装置具有晶体管/二极管对,其中源电极,栅电极,漏电极,阳极电极和阴极电极依次依次设置,晶体管的漏电极和阳极电极 二极管通过漏极/阳极公共电极布线连接并用作公共电极。
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公开(公告)号:US20150311329A1
公开(公告)日:2015-10-29
申请号:US14736665
申请日:2015-06-11
Inventor: SATOSHI NAKAZAWA , TETSUZO UEDA
IPC: H01L29/778 , H01L29/423 , H01L29/205
CPC classification number: H01L29/7781 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/42316 , H01L29/4236 , H01L29/42364 , H01L29/517 , H01L29/66462 , H01L29/7786 , H01L29/7789
Abstract: Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InxAlyGa1-(x+y)N layer on the InAlN layer, where 0
Abstract translation: 提供了实现更高电流密度和较低接触电阻之间的兼容性并且表现出优异性能的场效应晶体管(FET)及其制造方法。 FET包括:衬底上方的沟道层; 沟道层上方的InAlN层; 在InAlN层上的In x Al y Ga 1-(x + y)N层,其中0
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公开(公告)号:US20160307822A1
公开(公告)日:2016-10-20
申请号:US15196153
申请日:2016-06-29
Inventor: RYOSUKE USUI , TETSUZO UEDA
IPC: H01L23/473 , H01L23/495 , H01L49/02 , H01L23/053 , H01L23/528
CPC classification number: H01L23/473 , H01L23/053 , H01L23/49562 , H01L23/528 , H01L28/40 , H01L2924/0002 , H02M7/48 , H05K7/20927 , H01L2924/00
Abstract: A semiconductor device includes a semiconductor module including a semiconductor element, a passive element, a cooling member, a first conductive member and a second conductive member. The cooling member is disposed between the semiconductor module and the passive element. And a first conductive member and a second conductive member electrically connect the semiconductor module and the passive element. Furthermore, two or more aspects of at least one of the first conductive member and the second conductive member face the cooling member.
Abstract translation: 半导体器件包括半导体元件,半导体元件,无源元件,冷却元件,第一导电元件和第二导电元件。 冷却构件设置在半导体模块和无源元件之间。 并且第一导电构件和第二导电构件电连接半导体模块和无源元件。 此外,第一导电构件和第二导电构件中的至少一个的两个或多个方面面向冷却构件。
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公开(公告)号:US20160056245A1
公开(公告)日:2016-02-25
申请号:US14930628
申请日:2015-11-02
Inventor: YUSUKE KINOSHITA , SATOSHI TAMURA , TETSUZO UEDA
IPC: H01L29/205 , H01L29/66 , H01L29/808
CPC classification number: H01L29/205 , H01L29/1066 , H01L29/2003 , H01L29/201 , H01L29/432 , H01L29/66462 , H01L29/66916 , H01L29/66924 , H01L29/7786 , H01L29/8086
Abstract: A semiconductor device includes: a channel layer which is made of InpAlqGa1-p-qN (0≦p+q≦1, 0≦p, and 0≦q); a barrier layer which is formed on the channel layer and is made of InrAlsGa1-r-sN (0≦r+s≦1, 0≦r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of IntAluGa1-t-uN (0≦t+u≦1, 0≦t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of InxAlyGa1-x-yN (0≦x+y≦1, 0≦y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.
Abstract translation: 半导体器件包括:由InpAlqGa1-p-qN(0≦̸ p + q≦̸ 1,0& nlE; p和0≦̸ q)制成的沟道层; 阻挡层,其形成在沟道层上,并且由InrAlsGa1-r-sN(0< nlE; r + s≦̸ 1,0& nlE; r)制成,其带隙大于沟道层的带隙; 扩散抑制层,其被选择性地形成在阻挡层上并由IntAluGa1-t-uN(0< nlE; t + u≦̸ 1,0& nlE; t和s> u)制成; p型导电层,其形成在扩散抑制层上,由具有p型导电性的In x Al y Ga 1-x-y N(0< n 1; x + y≦̸ 1,0& 以及形成在p型导电层上的栅电极。
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公开(公告)号:US20150194483A1
公开(公告)日:2015-07-09
申请号:US14663140
申请日:2015-03-19
Inventor: RYO KAJITANI , TETSUZO UEDA , YOSHIHARU ANDA , NAOHIRO TSURUMI , SATOSHI NAKAZAWA
CPC classification number: H01L29/0611 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/404 , H01L29/51 , H01L29/66462 , H01L29/7786 , H01L29/78
Abstract: An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.
Abstract translation: 目的是通过减少电流崩溃来实现增益的增加,并减少Cgd和Rg。 根据本发明的半导体器件包括:衬底; 设置在所述基板上并由III族氮化物半导体构成的第一半导体层; 设置在第一半导体层上并由III族氮化物半导体构成的第二半导体层; 设置在所述第二半导体层上的栅电极,源电极和漏电极; 设置在所述第二半导体层上的第一场板电极; 以及设置在第一场极板电极上的第二场极板电极,其中第一场极板电极和第二场极板电极设置在栅电极和漏电极之间。
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公开(公告)号:US20150303293A1
公开(公告)日:2015-10-22
申请号:US14790064
申请日:2015-07-02
Inventor: KENICHIRO TANAKA , SHINICHI KOHDA , MASAHIRO ISHIDA , TETSUZO UEDA
IPC: H01L29/778 , H01L29/207 , H01L29/06 , H01L29/36 , H01L29/205
CPC classification number: H01L29/7787 , H01L29/0684 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/36 , H01L29/7786
Abstract: A field-effect transistor includes a codoped layer made of AlxGa1-xN (0≦x≦1) and formed on a p-type Si substrate, a GaN layer formed on the codoped layer, and an AlGaN layer formed on the GaN layer. The codoped layer contains C and Si as impurity elements. The impurity concentration of C in the codoped layer is equal to or higher than 5×1017/cm3. The impurity concentration of Si in the codoped layer is lower than the impurity concentration of C. The impurity concentration of C in the GaN layer is equal to or lower than 1×1017/cm3. The thickness of the GaN layer is equal to or greater than 0.75 μm.
Abstract translation: 场效应晶体管包括由Al x Ga 1-x N(0≦̸ x≦̸ 1)构成并且形成在p型Si衬底上的共掺层,在共掺层上形成的GaN层和形成在GaN层上的AlGaN层。 共掺层含有C和Si作为杂质元素。 共掺层中的C的杂质浓度等于或高于5×1017 / cm3。 共掺层中Si的杂质浓度低于C的杂质浓度.Ca层中的C的杂质浓度等于或低于1×1017 / cm3。 GaN层的厚度等于或大于0.75μm。
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公开(公告)号:US20150171173A1
公开(公告)日:2015-06-18
申请号:US14636163
申请日:2015-03-02
Inventor: HIDEKAZU UMEDA , MASAHIRO ISHIDA , TETSUZO UEDA , DAISUKE UEDA
IPC: H01L29/205 , H01L29/36 , H01L29/778 , H01L29/20
CPC classification number: H01L29/205 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L29/1066 , H01L29/155 , H01L29/2003 , H01L29/36 , H01L29/7786 , H01L29/86
Abstract: A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 Ωcm or more, and the internal region has a resistivity of 1000 Ωcm or more.
Abstract translation: 本公开的氮化物半导体结构包括半导体衬底和形成在半导体衬底上并包括多个氮化物半导体层的层。 半导体衬底从其包括多个氮化物半导体层的层的一侧开始依次具有表面区域和内部区域。 表面区域的电阻率为0.1Ω·cm〜(cm)以上,内部区域的电阻率为1000ΩΩ·cm以上。
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