公开(公告)号：US20180145020A1

公开(公告)日：2018-05-24

申请号：US15580457

申请日：2016-07-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHINICHI KOHDA ,  JUNICHI KIMURA ,  RYOSUKE USUI ,  TOMOHIDE OGURA ,  ATSUSHI WATANABE

IPC: H01L23/50 ,  H01L23/58 ,  H01L23/36 ,  H01L23/495

CPC classification number: H01L23/50 ,  H01L23/36 ,  H01L23/48 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/585 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/0603 ,  H01L2224/37147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H05K7/20 ,  H01L2924/00014

Abstract: This semiconductor device includes a semiconductor element mounted on a metal layer, first to third connection terminals that are provided on the semiconductor element, a first bus bar bonded to the first connection terminal, and a second bus bar bonded to the second connection terminal. The semiconductor element is bonded to the metal layer, and the first to third connection terminals are disposed on a top surface of the semiconductor element. One end of the first bus bar is bonded to the first connection terminal, another end of the first bus bar is an output unit, one end of the second bus bar is bonded to the second connection terminal, and another end of the second bus bar is bonded to the metal layer. A first surface of the semiconductor element and the second bus bar are at an identical potential.