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公开(公告)号:US20230412153A1
公开(公告)日:2023-12-21
申请号:US18461119
申请日:2023-09-05
Inventor: Yusuke KINOSHITA , Takashi ICHIRYU , Hidetoshi ISHIDA
Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
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公开(公告)号:US20230412154A1
公开(公告)日:2023-12-21
申请号:US18461126
申请日:2023-09-05
Inventor: Yusuke KINOSHITA , Takashi ICHIRYU , Hidetoshi ISHIDA
Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
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公开(公告)号:US20220271738A1
公开(公告)日:2022-08-25
申请号:US17626296
申请日:2020-07-10
Inventor: Yusuke KINOSHITA , Takashi ICHIRYU , Hidetoshi ISHIDA
Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.
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公开(公告)号:US20220310835A1
公开(公告)日:2022-09-29
申请号:US17612542
申请日:2020-05-14
Inventor: Takashi ICHIRYU , Yusuke KINOSHITA , Ryusuke KANOMATA , Masanori NOMURA , Hidetoshi ISHIDA
IPC: H01L29/778 , H01L29/10 , H01L29/20 , H01L29/205
Abstract: A bidirectional switch module includes a plurality of bidirectional switches and a mount board. Each of the plurality of bidirectional switches includes a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode. On the mount board, the plurality of bidirectional switches are mounted. In the bidirectional switch module, the plurality of bidirectional switches are connected in parallel.
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公开(公告)号:US20200027814A1
公开(公告)日:2020-01-23
申请号:US16497744
申请日:2018-03-27
Inventor: Takashi ICHIRYU , Masanori NOMURA , Yusuke KINOSHITA , Hidetoshi ISHIDA , Yasuhiro YAMADA
IPC: H01L23/367 , H01L23/373 , H01L23/29 , H01L23/00 , H01L23/31 , H01L23/532
Abstract: A semiconductor device includes a supporting substrate, a semiconductor chip, a resin member, and a heat-dissipating metal layer. The supporting substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the supporting substrate. The semiconductor chip includes a plurality of electrodes. The semiconductor chip is bonded to the supporting substrate on one side thereof with the first surface. The resin member has a first surface and a second surface located opposite from each other in a thickness direction defined for the resin member. The resin member covers at least a side surface of the supporting substrate and a side surface of the semiconductor chip. The heat-dissipating metal layer is arranged in contact with the supporting substrate and the resin member to cover the second surface of the supporting substrate and the second surface of the resin member at least partially.
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公开(公告)号:US20170300147A1
公开(公告)日:2017-10-19
申请号:US15481974
申请日:2017-04-07
Inventor: Yoshihiro TOMITA , Koji KAWAKITA , Koichi HIRANO , Masanori NOMURA , Susumu SAWADA , Takashi ICHIRYU
CPC classification number: G06F3/044 , G01L1/205 , G06F3/045 , G06F3/047 , G06F2203/04102 , G06F2203/04103
Abstract: A flexible touch sensor comprises: a first sheet material that has a first major surface, and that has a cushioning property; a second sheet material that includes a conductive material, and that is disposed on the first major surface of the first sheet material; and a conductive wire that is disposed on the first major surface of the first sheet material, and that is sunk into the first sheet material.
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公开(公告)号:US20220224321A1
公开(公告)日:2022-07-14
申请号:US17614716
申请日:2020-04-28
Inventor: Yusuke KINOSHITA , Takashi ICHIRYU , Ryusuke KANOMATA , Hidetoshi ISHIDA
IPC: H03K17/04
Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.
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公开(公告)号:US20210408934A1
公开(公告)日:2021-12-30
申请号:US17290489
申请日:2019-08-23
Inventor: Yusuke KINOSHITA , Yasuhiro YAMADA , Takashi ICHIRYU , Masanori NOMURA , Hidetoshi ISHIDA
IPC: H02M7/483 , H02M1/08 , H01L29/778
Abstract: A GaN layer is formed over the substrate. An AlGaN layer is formed on the GaN layer. A first source electrode, a first gate electrode, a second gate electrode, and a second source electrode are formed on or over the AlGaN layer. A first p-type Alx1Ga1-x1N layer where 0≤x1
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