公开(公告)号：US20230412153A1

公开(公告)日：2023-12-21

申请号：US18461119

申请日：2023-09-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Takashi ICHIRYU ,  Hidetoshi ISHIDA

IPC: H03K3/012 ,  H03K17/04

CPC classification number: H03K3/012 ,  H03K17/04

Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.

公开(公告)号：US20210028303A1

公开(公告)日：2021-01-28

申请号：US16982210

申请日：2019-03-22

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Asamira SUZUKI ,  Hidetoshi ISHIDA

IPC: H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66

Abstract: A plurality of semiconductor portions are arranged in a first direction to be spaced apart from each other. A heterojunction of each of the plurality of semiconductor portions extends in a second direction perpendicular to a first direction aligned with a c-axis of a first nitride semiconductor portion. Each of a plurality of first electrodes overlaps with an associated one of the plurality of semiconductor portions in a third direction perpendicular to both of the first direction and the second direction, and is directly electrically connected to the heterojunction of the associated semiconductor portion. Each of the plurality of second electrodes is located, with respect to an associated one of the plurality of semiconductor portions, opposite in the third direction from one of the plurality of first electrodes that overlaps with the associated semiconductor portion, and is directly electrically connected to the heterojunction of the associated semiconductor portion.

公开(公告)号：US20200044066A1

公开(公告)日：2020-02-06

申请号：US16498366

申请日：2018-03-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Asamira SUZUKI ,  Hiroaki UENO ,  Hidetoshi ISHIDA

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/04

Abstract: A semiconductor device includes a substrate, a semiconductor portion, a first electrode, and a second electrode. The substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the substrate. The semiconductor portion is provided on the first surface of the substrate. The semiconductor portion includes a heterojunction defining a junction between a first compound semiconductor portion and a second compound semiconductor portion and intersecting with a first direction defined along the first surface of the substrate. The first electrode and the second electrode are arranged on a first end surface of the semiconductor portion and on a second end surface of the semiconductor portion, respectively, in a second direction defined along the first surface of the substrate and aligned with a direction in which the heterojunction extends. The first electrode and the second electrode are electrically connected to the heterojunction.

公开(公告)号：US20220337239A1

公开(公告)日：2022-10-20

申请号：US17633160

申请日：2020-10-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Hidetoshi ISHIDA ,  Hiroyuki HANDA ,  Yuji KUDOH ,  Satoshi NAKAZAWA

IPC: H03K17/687 ,  G01R31/26

Abstract: A switch system includes a bidirectional switch, a first gate driver circuit, a second gate driver circuit, a control unit, a first decision unit, and a second decision unit. The bidirectional switch includes a first source, a second source, a first gate, and a second gate. The first decision unit determines, based on a voltage at the first gate and a first threshold voltage, a state of the first gate in a first period in which a signal to turn OFF the first gate is output from the control unit to the first gate driver circuit. The second decision unit determines, based on a voltage at the second gate and a second threshold voltage, a state of the second gate in a second period in which a signal to turn OFF the second gate is output from the control unit to the second gate driver circuit.

公开(公告)号：US20220310835A1

公开(公告)日：2022-09-29

申请号：US17612542

申请日：2020-05-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takashi ICHIRYU ,  Yusuke KINOSHITA ,  Ryusuke KANOMATA ,  Masanori NOMURA ,  Hidetoshi ISHIDA

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205

Abstract: A bidirectional switch module includes a plurality of bidirectional switches and a mount board. Each of the plurality of bidirectional switches includes a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode. On the mount board, the plurality of bidirectional switches are mounted. In the bidirectional switch module, the plurality of bidirectional switches are connected in parallel.

公开(公告)号：US20220224321A1

公开(公告)日：2022-07-14

申请号：US17614716

申请日：2020-04-28

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Takashi ICHIRYU ,  Ryusuke KANOMATA ,  Hidetoshi ISHIDA

IPC: H03K17/04

Abstract: A speed-up circuit is configured to be provided between a power supply terminal and a gate of a semiconductor switching element. An impedance element is configured to be provided between a signal input terminal and a node, the node being between the speed-up circuit and the gate of the semiconductor switching element. In the speed-up circuit, a second field effect transistor is connected in series to a first field effect transistor and is configured to be connected to the gate of the semiconductor switching element. The impedance element has an impedance higher than an impedance of the speed-up circuit when both the first field effect transistor and the second field effect transistor are in an ON state.

公开(公告)号：US20210408934A1

公开(公告)日：2021-12-30

申请号：US17290489

申请日：2019-08-23

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Yusuke KINOSHITA ,  Yasuhiro YAMADA ,  Takashi ICHIRYU ,  Masanori NOMURA ,  Hidetoshi ISHIDA

IPC: H02M7/483 ,  H02M1/08 ,  H01L29/778

Abstract: A GaN layer is formed over the substrate. An AlGaN layer is formed on the GaN layer. A first source electrode, a first gate electrode, a second gate electrode, and a second source electrode are formed on or over the AlGaN layer. A first p-type Alx1Ga1-x1N layer where 0≤x1

公开(公告)号：US20210134963A1

公开(公告)日：2021-05-06

申请号：US17256475

申请日：2019-06-12

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Masanori NOMURA ,  Hiroaki UENO ,  Yusuke KINOSHITA ,  Yasuhiro YAMADA ,  Hidetoshi ISHIDA

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/808 ,  H01L29/43

Abstract: A bidirectional switch element includes: a substrate; an AlzGa1-zN layer; an AlbGa1-bN layer; a first source electrode; a first gate electrode; a second gate electrode; a second source electrode; a p-type Alx1Ga1-x1N layer; a p-type Alx2Ga1-x2N layer; an AlyGa1-yN layer; and an AlwGa1-wN layer. The AlzGa1-zN layer is formed over the substrate. The AlbGa1-bN layer is formed on the AlzGa1-zN layer. The AlyGa1-yN layer is interposed between the substrate and the AlzGa1-zN layer. The AlwGa1-wN layer is interposed between the substrate and the AlyGa1-yN layer and has a higher C concentration than the AlyGa1-yN layer.

公开(公告)号：US20230412154A1

公开(公告)日：2023-12-21

申请号：US18461126

申请日：2023-09-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Takashi ICHIRYU ,  Hidetoshi ISHIDA

IPC: H03K3/012 ,  H03K17/04

CPC classification number: H03K3/012 ,  H03K17/04

Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.

公开(公告)号：US20220271738A1

公开(公告)日：2022-08-25

申请号：US17626296

申请日：2020-07-10

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yusuke KINOSHITA ,  Takashi ICHIRYU ,  Hidetoshi ISHIDA

IPC: H03K3/012 ,  H03K17/04

Abstract: A gate drive circuit includes: an input terminal; a first circuit path inserted into a line connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path. The first circuit path includes a gate resistor (Rgon). The second circuit path includes a first capacitor and a first resistor connected in series. The third circuit path includes a second capacitor and a second resistor connected in series. The second capacitor has a capacitance value greater than a capacitance value of the first capacitor. The second resistor has a resistance value greater than a resistance value of the first resistor. The gate resistor (Rgon) has a resistance value greater than the resistance value of the second resistor.