公开(公告)号：US06395618B2

公开(公告)日：2002-05-28

申请号：US09745071

申请日：2000-12-19

申请人： Paolo Vergani ,  Ilaria Gelmi ,  Pietro Montanini ,  Marco Ferrera ,  Laura Castoldi

发明人： Paolo Vergani ,  Ilaria Gelmi ,  Pietro Montanini ,  Marco Ferrera ,  Laura Castoldi

IPC分类号： H01L2176

CPC分类号： H01L21/764

摘要： The method is based on the use of an etching mask comprising silicon carbide or titanium nitride for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a masking layer comprising silicon carbide or titanium nitride; defining photolithographically the masking layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.

摘要翻译： 该方法基于使用包含碳化硅或氮化钛的蚀刻掩模来去除牺牲区域。 在制造集成半导体材料结构的情况下，执行以下步骤：在半导体材料的衬底上形成氧化硅牺牲区; 生长伪外延层; 形成电子电路部件; 沉积包含碳化硅或氮化钛的掩模层; 光刻地限定掩模层，以形成包含要形成的微结构的形貌的蚀刻掩模; 利用蚀刻掩模，在伪外延层中形成直到牺牲区域的沟槽，以横向限定微结构; 并通过沟槽去除牺牲区域。

公开(公告)号：US06197655B1

公开(公告)日：2001-03-06

申请号：US09113466

申请日：1998-07-10

申请人： Pietro Montanini ,  Marco Ferrera ,  Laura Castoldi ,  Ilaria Gelmi

发明人： Pietro Montanini ,  Marco Ferrera ,  Laura Castoldi ,  Ilaria Gelmi

IPC分类号： H01L2176

CPC分类号： B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

摘要： The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a silicon carbide layer; defining photolithographically the silicon carbon layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.

摘要翻译： 该方法基于使用碳化硅掩模去除牺牲区域。 在制造集成半导体材料结构的情况下，执行以下步骤：在半导体材料的衬底上形成氧化硅牺牲区; 生长伪外延层; 形成电子电路部件; 沉积碳化硅层; 光刻地定义硅碳层，以形成含有要形成的微结构的形貌的蚀刻掩模; 利用蚀刻掩模，在伪外延层中形成直到牺牲区域的沟槽，以横向限定微结构; 并通过沟槽去除牺牲区域。

公开(公告)号：US06331444B1

公开(公告)日：2001-12-18

申请号：US09499919

申请日：2000-02-08

申请人： Paolo Ferrari ,  Benedetto Vigna ,  Pietro Montanini ,  Laura Castoldi ,  Marco Ferrera

发明人： Paolo Ferrari ,  Benedetto Vigna ,  Pietro Montanini ,  Laura Castoldi ,  Marco Ferrera

IPC分类号： H01L2100

CPC分类号： B81B3/0072 ,  B81B2203/033 ,  B81C1/00666 ,  B81C2201/017 ,  G01P15/0802 ,  G01P2015/0828

摘要： On a substrate of semiconductor material, a sacrificial region is formed and an epitaxial layer is grown; a stress release trench is formed, surrounding an area of the epitaxial layer, where an integrated electromechanical microstructure is to be formed; the wafer is then heat treated, to release residual stress. Subsequently, the stress release trench is filled with a sealing region of dielectric material, and integrated components are formed. Finally, inside the area surrounded by the sealing region, a microstructure definition trench is formed, and the sacrificial region is removed, thus obtaining an integrated microstructure with zero residual stress.

摘要翻译： 在半导体材料的衬底上，形成牺牲区，生长外延层; 形成应力释放沟槽，围绕将要形成集成的机电微结构的外延层的区域; 然后对晶片进行热处理，以释放残余应力。 随后，应力释放槽填充有电介质材料的密封区域，形成集成的部件。 最后，在由密封区域包围的区域内，形成微结构定义沟槽，去除牺牲区域，从而获得零残余应力的集成微结构。