公开(公告)号：US06395618B2

公开(公告)日：2002-05-28

申请号：US09745071

申请日：2000-12-19

申请人： Paolo Vergani ,  Ilaria Gelmi ,  Pietro Montanini ,  Marco Ferrera ,  Laura Castoldi

发明人： Paolo Vergani ,  Ilaria Gelmi ,  Pietro Montanini ,  Marco Ferrera ,  Laura Castoldi

IPC分类号： H01L2176

CPC分类号： H01L21/764

摘要： The method is based on the use of an etching mask comprising silicon carbide or titanium nitride for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a masking layer comprising silicon carbide or titanium nitride; defining photolithographically the masking layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.

摘要翻译： 该方法基于使用包含碳化硅或氮化钛的蚀刻掩模来去除牺牲区域。 在制造集成半导体材料结构的情况下，执行以下步骤：在半导体材料的衬底上形成氧化硅牺牲区; 生长伪外延层; 形成电子电路部件; 沉积包含碳化硅或氮化钛的掩模层; 光刻地限定掩模层，以形成包含要形成的微结构的形貌的蚀刻掩模; 利用蚀刻掩模，在伪外延层中形成直到牺牲区域的沟槽，以横向限定微结构; 并通过沟槽去除牺牲区域。

公开(公告)号：US06197655B1

公开(公告)日：2001-03-06

申请号：US09113466

申请日：1998-07-10

申请人： Pietro Montanini ,  Marco Ferrera ,  Laura Castoldi ,  Ilaria Gelmi

发明人： Pietro Montanini ,  Marco Ferrera ,  Laura Castoldi ,  Ilaria Gelmi

IPC分类号： H01L2176

CPC分类号： B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

摘要： The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region of silicon oxide on a substrate of semiconductor material; growing a pseudo-epitaxial layer; forming electronic circuit components; depositing a silicon carbide layer; defining photolithographically the silicon carbon layer so as to form an etching mask containing the topography of a microstructure to be formed; with the etching mask, forming trenches in the pseudo-epitaxial layer as far as the sacrificial region so as to laterally define the microstructure; and removing the sacrificial region through the trenches.

摘要翻译： 该方法基于使用碳化硅掩模去除牺牲区域。 在制造集成半导体材料结构的情况下，执行以下步骤：在半导体材料的衬底上形成氧化硅牺牲区; 生长伪外延层; 形成电子电路部件; 沉积碳化硅层; 光刻地定义硅碳层，以形成含有要形成的微结构的形貌的蚀刻掩模; 利用蚀刻掩模，在伪外延层中形成直到牺牲区域的沟槽，以横向限定微结构; 并通过沟槽去除牺牲区域。

公开(公告)号：US20060068554A1

公开(公告)日：2006-03-30

申请号：US11230292

申请日：2005-09-19

申请人： Pietro Montanini ,  Giovanna Germani ,  Ilaria Gelmi ,  Marta Mottura

发明人： Pietro Montanini ,  Giovanna Germani ,  Ilaria Gelmi ,  Marta Mottura

IPC分类号： H01L21/336

CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/31116

摘要： The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

公开(公告)号：US08486741B2

公开(公告)日：2013-07-16

申请号：US13481680

申请日：2012-05-25

申请人： Pietro Montanini ,  Giovanna Germani ,  Ilaria Gelmi ,  Marta Mottura

发明人： Pietro Montanini ,  Giovanna Germani ,  Ilaria Gelmi ,  Marta Mottura

IPC分类号： H01L21/00 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/0334 ,  H01L21/31116

摘要： The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

摘要翻译： 所描述的工艺允许在包括形成在衬底上的支撑衬底和多层的结构中蚀刻沟槽，用于定义集成光学器件的波导，并且包括通过掩蔽结构在多层中的选择性等离子体侵蚀 对应于要蚀刻的沟槽的多层的未覆盖区域。 这样的掩模结构是通过在多层上形成金属材料掩模而获得的，该多层不会覆盖与待蚀刻的沟槽相对应的区域，并且形成非金属材料（例如光致抗蚀剂）的掩模，其上留下未覆盖的区域， 至少部分区域和金属材料掩模的边缘部分。

公开(公告)号：US08344466B2

公开(公告)日：2013-01-01

申请号：US12850548

申请日：2010-08-04

申请人： Pietro Corona ,  Stefano Losa ,  Ilaria Gelmi ,  Roberto Campedelli

发明人： Pietro Corona ,  Stefano Losa ,  Ilaria Gelmi ,  Roberto Campedelli

IPC分类号： H01L29/84 ,  H01L21/02

CPC分类号： B81C1/00476 ,  B81B2201/0264 ,  B81B2203/0109 ,  B81B2203/0127 ,  B81C1/00047 ,  B81C2201/0109

摘要： A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity. Other embodiments are directed to MEMS devices and pressure sensors.

摘要翻译： 一种用于制造MEMS器件的方法，其中底部硅区域形成在衬底上和绝缘层上; 电介质的牺牲区形成在底部区域上; 半导体材料的膜区域在牺牲区域上外延生长; 将膜区域向下挖到牺牲区域以形成通孔; 孔的侧壁和底部以保形方式完全涂覆有多孔材料层; 牺牲区域的至少一部分被选择性地通过多孔材料层去除并形成空腔; 并且孔填充有填充材料，以便形成悬浮在空腔上方的整体膜。 其它实施例涉及MEMS器件和压力传感器。

公开(公告)号：US06696364B2

公开(公告)日：2004-02-24

申请号：US10214998

申请日：2002-08-08

申请人： Ilaria Gelmi ,  Simone Sassolini ,  Stefano Pozzi ,  Massimo Garavaglia

发明人： Ilaria Gelmi ,  Simone Sassolini ,  Stefano Pozzi ,  Massimo Garavaglia

IPC分类号： H01L21302

CPC分类号： B81C1/0088

摘要： A method for manipulating MEMS devices integrated on a semiconductor wafer and intended to be diced one from the other includes bonding of the semiconductor wafer including the MEMS devices on a support with interposition of a bonding sheet. The method may also include completely cutting or dicing of the semiconductor wafer into a plurality of independent MEMS devices, and processing the MEMS devices diced and bonded on the support in a treatment environment for semiconductor wafers. A support for manipulating MEMS devices is also included.

摘要翻译： 用于操作集成在半导体晶片上并且要彼此切割的MEMS器件的方法包括将包括MEMS器件的半导体晶片粘合在支撑体上并插入粘结片。 该方法还可以包括将半导体晶片完全切割或切割成多个独立的MEMS器件，以及在半导体晶片的处理环境中处理在支撑体上切割和结合的MEMS器件。 还包括用于操纵MEMS器件的支持。

公开(公告)号：US20110031567A1

公开(公告)日：2011-02-10

申请号：US12850548

申请日：2010-08-04

申请人： Pietro Corona ,  Stefano Losa ,  Ilaria Gelmi ,  Roberto Campedelli

发明人： Pietro Corona ,  Stefano Losa ,  Ilaria Gelmi ,  Roberto Campedelli

IPC分类号： H01L29/84 ,  H01L21/02

CPC分类号： B81C1/00476 ,  B81B2201/0264 ,  B81B2203/0109 ,  B81B2203/0127 ,  B81C1/00047 ,  B81C2201/0109

摘要： A process for manufacturing a MEMS device, wherein a bottom silicon region is formed on a substrate and on an insulating layer; a sacrificial region of dielectric is formed on the bottom region; a membrane region, of semiconductor material, is epitaxially grown on the sacrificial region; the membrane region is dug down to the sacrificial region so as to form through apertures; the side wall and the bottom of the apertures are completely coated in a conformal way with a porous material layer; at least one portion of the sacrificial region is selectively removed through the porous material layer and forms a cavity; and the apertures are filled with filling material so as to form a monolithic membrane suspended above the cavity.

摘要翻译： 一种用于制造MEMS器件的方法，其中底部硅区域形成在衬底上和绝缘层上; 电介质的牺牲区形成在底部区域上; 半导体材料的膜区域在牺牲区域上外延生长; 将膜区域向下挖到牺牲区域以形成通孔; 孔的侧壁和底部以保形方式完全涂覆有多孔材料层; 牺牲区域的至少一部分被选择性地通过多孔材料层去除并形成空腔; 并且孔填充有填充材料，以便形成悬浮在空腔上方的整体膜。