公开(公告)号：US20120092119A1

公开(公告)日：2012-04-19

申请号：US12906006

申请日：2010-10-15

申请人： Vassili Kireev ,  Parag Upadhyaya ,  Mark J. Marlett

发明人： Vassili Kireev ,  Parag Upadhyaya ,  Mark J. Marlett

IPC分类号： H01F5/00

CPC分类号： H01F17/0013 ,  H01F2017/0073 ,  Y10T29/4902

摘要： A symmetrical inductor includes pairs of half-loops, first and second terminal electrodes, and a center-tap electrode. The half-loop pairs are in respective conductive layers of an integrated circuit. Each half-loop pair includes a first and second half-loop in the respective conductive layer. The first and second terminal electrodes are in a first conductive layer, and the center-tap electrode is in a second conductive layer. The first terminal electrode and the center-tap electrode are coupled through a first series combination that includes the first half-loop of each half-loop pair. The second terminal electrode and the center-tap electrode are coupled through a second series combination that includes the second half-loop of each half-loop pair.

摘要翻译： 对称电感器包括一对半环，第一和第二端子电极以及中心抽头电极。 半环对在集成电路的各个导电层​​中。 每个半环对在相应导电层中包括第一和第二半环。 第一和第二端子电极在第一导电层中，中心抽头电极处于第二导电层中。 第一端子电极和中心抽头电极通过包括每个半环对的第一半环的第一串联组合耦合。 第二端子电极和中心抽头电极通过包括每个半环对的第二半环的第二串联组合耦合。

公开(公告)号：US09136690B1

公开(公告)日：2015-09-15

申请号：US13221219

申请日：2011-08-30

申请人： Parag Upadhyaya ,  Mark J. Marlett

发明人： Parag Upadhyaya ,  Mark J. Marlett

IPC分类号： H02H1/06

CPC分类号： H02H1/06 ,  H01L27/0266

摘要： A termination circuit configured to provide electrostatic discharge (ESD) protection is provided. Termination sub-circuits are coupled in parallel, each including respective pull-up and pull-down circuits. Each pull-up circuit has two transistors of a first type coupled in series between a data input and Vdd, a gate of one of the two transistors being coupled to a control input and a gate of the other one of the two transistors being coupled to a first enable input of the termination sub-circuit. Each pull-down circuit has two transistors of a second type coupled in series between the data input and Vss or ground, a gate of one of the two transistors being coupled to the control input and the gate of the other one of the two transistors being coupled to a second enable input of the termination sub-circuit.

摘要翻译： 提供了一种被配置为提供静电放电（ESD）保护的终端电路。 端接子电路并联耦合，每个子电路包括相应的上拉和下拉电路。 每个上拉电路具有串联耦合在数据输入端和Vdd之间的两个第一类型的晶体管，两个晶体管中的一个晶体管的栅极耦合到控制输入，并且两个晶体管中的另一个晶体管的栅极耦合到 终端子电路的第一使能输入。 每个下拉电路具有串联耦合在数据输入端和Vss或接地之间的两个第二类型的晶体管，两个晶体管中的一个晶体管的栅极耦合到控制输入端，而两个晶体管中另一个晶体管的栅极为 耦合到终端子电路的第二使能输入。

公开(公告)号：US20120212315A1

公开(公告)日：2012-08-23

申请号：US13463497

申请日：2012-05-03

申请人： Vassili Kireev ,  Parag Upadhyaya ,  Mark J. Marlett

发明人： Vassili Kireev ,  Parag Upadhyaya ,  Mark J. Marlett

IPC分类号： H01F27/29 ,  H01F41/00

CPC分类号： H01F17/0013 ,  H01F2017/0073 ,  Y10T29/4902

摘要： A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.

摘要翻译： 对称电感器包括具有多个导电层的集成电路。 第一环设置在导电层的上层中，并且至少两个绑扎环分别设置在至少两层导电层中。 捆扎环与第一环串联耦合，并且至少两层位于上层下方。 第二环设置在上层中并串联耦合到至少两个带状环。 第一端子电极耦合到第一环路，并且第二端子电极耦合到第二环路。 中心抽头电极耦合到至少两个绑扎环。

公开(公告)号：US08358192B2

公开(公告)日：2013-01-22

申请号：US13463497

申请日：2012-05-03

申请人： Vassili Kireev ,  Parag Upadhyaya ,  Mark J. Marlett

发明人： Vassili Kireev ,  Parag Upadhyaya ,  Mark J. Marlett

IPC分类号： H01F27/29 ,  H01F5/00 ,  H01F27/28 ,  H01F7/06

CPC分类号： H01F17/0013 ,  H01F2017/0073 ,  Y10T29/4902

摘要： A symmetrical inductor includes an integrated circuit having a plurality of conductive layers. A first loop is disposed in an upper layer of the conductive layers, and at least two strapped loops are disposed in at least two layers of the conductive layers, respectively. The strapped loops are coupled in series to the first loop, and the at least two layers are below the upper layer. A second loop is disposed in the upper layer and is coupled in series to the at least two strapped loops. A first terminal electrode is coupled to the first loop, and a second terminal electrode is coupled to the second loop. A center-tap electrode is coupled to the at least two strapped loops.

摘要翻译： 对称电感器包括具有多个导电层的集成电路。 第一环设置在导电层的上层中，并且至少两个绑扎环分别设置在至少两层导电层中。 捆扎环与第一环串联耦合，并且至少两层位于上层下方。 第二环设置在上层中并串联耦合到至少两个带状环。 第一端子电极耦合到第一环路，并且第二端子电极耦合到第二环路。 中心抽头电极耦合到至少两个绑扎环。

公开(公告)号：US20120241904A1

公开(公告)日：2012-09-27

申请号：US13052293

申请日：2011-03-21

申请人： Zhaoyin D. Wu ,  Xuewen Jiang ,  Parag Upadhyaya

发明人： Zhaoyin D. Wu ,  Xuewen Jiang ,  Parag Upadhyaya

IPC分类号： H01L27/10

CPC分类号： H01L27/08

摘要： An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.

摘要翻译： 在半导体集成电路（IC）中实现的电感器结构可以包括导体材料的线圈，其包括位于线圈长度的中点处的中心端子。 线圈可相对于将中心线平分的中心线对称。 线圈可以包括第一差分端子和第二差分端子，每个端子位于线圈的端部并且与中心端子相对。 电感器结构可以包括围绕线圈的隔离环。 在一些情况下，电感器结构可以包括定位在中心线上的导电材料的返回线。

公开(公告)号：US20120092081A1

公开(公告)日：2012-04-19

申请号：US12906017

申请日：2010-10-15

申请人： Parag Upadhyaya ,  Vassili Kireev

发明人： Parag Upadhyaya ,  Vassili Kireev

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1262 ,  H03B5/1265 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/0266

摘要： A tunable resonant circuit includes first and second capacitors that provide a matched capacitance between first and second electrodes of the first and second capacitors. A deep-well arrangement includes a first well disposed within a second well in a substrate. The first and second capacitors are each disposed on the first well. Two channel electrodes of a first transistor are respectively coupled to the second electrode of the first capacitor and the second electrode of the second capacitor. Two channel electrodes of a second transistor are respectively coupled to the second electrode of the first capacitor and to ground. Two channel electrodes of the third transistor are respectively coupled to the second electrode of the second capacitor and to ground. The gate electrodes of the first, second, and third transistors are responsive to a tuning signal, and an inductor is coupled between the first electrodes of the first and second capacitors.

摘要翻译： 可调谐谐振电路包括在第一和第二电容器的第一和第二电极之间提供匹配电容的第一和第二电容器。 深井布置包括设置在基板中的第二井内的第一井。 第一和第二电容器各自设置在第一阱上。 第一晶体管的两沟道电极分别耦合到第一电容器的第二电极和第二电容器的第二电极。 第二晶体管的两沟道电极分别耦合到第一电容器的第二电极并接地。 第三晶体管的两沟道电极分别耦合到第二电容器的第二电极并接地。 第一，第二和第三晶体管的栅电极响应于调谐信号，并且电感器耦合在第一和第二电容器的第一电极之间。

公开(公告)号：US08592943B2

公开(公告)日：2013-11-26

申请号：US13052293

申请日：2011-03-21

申请人： Zhaoyin D. Wu ,  Xuewen Jiang ,  Parag Upadhyaya

发明人： Zhaoyin D. Wu ,  Xuewen Jiang ,  Parag Upadhyaya

IPC分类号： H01L21/00

CPC分类号： H01L27/08

摘要： An inductor structure implemented within a semiconductor integrated circuit (IC) can include a coil of conductive material that includes a center terminal located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline bisecting the center terminal. The coil can include a first differential terminal and a second differential terminal each located at an end of the coil and opposite the center terminal. The inductor structure can include an isolation ring surrounding the coil. In some cases, the inductor structure can include a return line of conductive material positioned on the center line.

摘要翻译： 在半导体集成电路（IC）中实现的电感器结构可以包括导体材料的线圈，其包括位于线圈长度的中点处的中心端子。 线圈可相对于将中心线平分的中心线对称。 线圈可以包括第一差分端子和第二差分端子，每个端子位于线圈的端部并且与中心端子相对。 电感器结构可以包括围绕线圈的隔离环。 在一些情况下，电感器结构可以包括定位在中心线上的导电材料的返回线。

公开(公告)号：US20130181783A1

公开(公告)日：2013-07-18

申请号：US13350501

申请日：2012-01-13

申请人： Parag Upadhyaya

发明人： Parag Upadhyaya

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1293

摘要： A resonator circuit enabling temperature compensation includes an inductor coupled between a first node and a second node of the resonator circuit; a capacitor circuit coupled between the first node and the second node; and a temperature compensation circuit coupled between the first node and the second node. The temperature compensation circuit comprises a varactor coupled to receive a temperature control signal that sets the capacitance of the varactor. A method of generating a resonating output is also disclosed.

摘要翻译： 能够进行温度补偿的谐振器电路包括耦合在谐振器电路的第一节点和第二节点之间的电感器; 耦合在所述第一节点和所述第二节点之间的电容器电路; 以及耦合在第一节点和第二节点之间的温度补偿电路。 温度补偿电路包括耦合以接收设置变容二极管的电容的温度控制信号的变容二极管。 还公开了一种产生谐振输出的方法。

公开(公告)号：US08941974B2

公开(公告)日：2015-01-27

申请号：US13229207

申请日：2011-09-09

申请人： Zhaoyin D. Wu ,  Parag Upadhyaya ,  Xuewen Jiang

发明人： Zhaoyin D. Wu ,  Parag Upadhyaya ,  Xuewen Jiang

IPC分类号： H01G4/008 ,  H01G4/228 ,  H01G4/005 ,  H01L49/02

CPC分类号： H01L28/86 ,  Y10T29/43

摘要： An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor includes a first plurality of conductive digits and a second plurality of conductive digits positioned in an interlocking manner with the first plurality of conductive digits, such that an interdigitated structure is formed. The first plurality of conductive digits and the second plurality of conductive digits collectively form a set of digits, where the width of a first digit in the set of digits is non-uniform with respect to a second digit in the set of digits.

摘要翻译： 公开了具有变化宽度的数字的交错电容器。 电容器的一个实施例包括以与第一多个导电数字互锁的方式定位的第一多个导电数字和第二多个导电数字，使得形成叉指结构。 第一组多个导电数字和第二多个导电数字共同形成一组数字，其中数字组中第一个数字的宽度相对于该组数字中的第二个数字是不均匀的。

公开(公告)号：US08717115B2

公开(公告)日：2014-05-06

申请号：US13350501

申请日：2012-01-13

申请人： Parag Upadhyaya

发明人： Parag Upadhyaya

IPC分类号： H03L1/00

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1293

摘要： A resonator circuit enabling temperature compensation includes an inductor coupled between a first node and a second node of the resonator circuit; a capacitor circuit coupled between the first node and the second node; and a temperature compensation circuit coupled between the first node and the second node. The temperature compensation circuit comprises a varactor coupled to receive a temperature control signal that sets the capacitance of the varactor. A method of generating a resonating output is also disclosed.

摘要翻译： 能够进行温度补偿的谐振器电路包括耦合在谐振器电路的第一节点和第二节点之间的电感器; 耦合在所述第一节点和所述第二节点之间的电容器电路; 以及耦合在第一节点和第二节点之间的温度补偿电路。 温度补偿电路包括耦合以接收设置变容二极管的电容的温度控制信号的变容二极管。 还公开了一种产生谐振输出的方法。