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公开(公告)号:US07084427B2
公开(公告)日:2006-08-01
申请号:US10250175
申请日:2003-06-10
申请人: Patricia Argandona , Faisal Azam , Andrew Lu , Helen Wang
发明人: Patricia Argandona , Faisal Azam , Andrew Lu , Helen Wang
IPC分类号: H01L23/58
CPC分类号: H01L22/34
摘要: The systems and methods enable the determination of the magnitude and direction of overlay of at least two elements in two layers. Overlay measurements along two axes can be obtained using four probe pads and without requiring a decoder. Overlay measurements along a single axis can be obtained using three probe pads and without requiring a decoder. The systems and methods according to this invention require less space and are more time efficient than conventional measurement structures. In the systems and methods of this invention, offsets in a direction are calculated from resistance measurements.
摘要翻译: 这些系统和方法使得能够确定两层中至少两个元素的叠加的大小和方向。 可以使用四个探针焊盘获得两个轴上的叠加测量值,无需解码器。 使用三个探针焊盘可以获得沿着单个轴的覆盖测量,而不需要解码器。 根据本发明的系统和方法需要更少的空间并且比常规测量结构更节约时间。 在本发明的系统和方法中,根据电阻测量计算方向的偏移。
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公开(公告)号:US20050019966A1
公开(公告)日:2005-01-27
申请号:US10250175
申请日:2003-06-10
申请人: Patricia Argandona , Faisal Azam , Andrew Lu , Helen Wang
发明人: Patricia Argandona , Faisal Azam , Andrew Lu , Helen Wang
IPC分类号: H01L23/544 , G01R31/26
CPC分类号: H01L22/34
摘要: The systems and methods enable the determination of the magnitude and direction of overlay of at least two elements in two layers. Overlay measurements along two axes can be obtained using four probe pads and without requiring a decoder. Overlay measurements along a single axis can be obtained using three probe pads and without requiring a decoder. The systems and methods according to this invention require less space and are more time efficient than conventional measurement structures. In the systems and methods of this invention, offsets in a direction are calculated from resistance measurements.
摘要翻译: 这些系统和方法使得能够确定两层中至少两个元素的叠加的大小和方向。 可以使用四个探针焊盘获得两个轴上的叠加测量值,无需解码器。 使用三个探针焊盘可以获得沿着单个轴的覆盖测量,而不需要解码器。 根据本发明的系统和方法需要更少的空间并且比常规测量结构更节约时间。 在本发明的系统和方法中,根据电阻测量计算方向的偏移。
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公开(公告)号:US07550303B2
公开(公告)日:2009-06-23
申请号:US11279534
申请日:2006-04-12
申请人: Patricia Argandona , Faisal Azam , Andrew Lu , Helen Wang
发明人: Patricia Argandona , Faisal Azam , Andrew Lu , Helen Wang
CPC分类号: H01L22/34
摘要: Method for measuring misalignment between at least two layers of an integrated circuit. The method includes applying a current between a plurality of probe members in a first layer, wherein a first probe member and a second probe member of the plurality of probe members are substantially aligned along a first axis and partially overlap an overlay target in a second layer, measuring a voltage across the plurality of probe members wherein at least a voltage across the first probe member and a third probe member disposed perpendicular to the first axis and a voltage across the second probe member and the third probe member are measured, and determining an amount of misalignment between the first layer and the second layer along at least one of the first axis and the second axis based on the measuring steps.
摘要翻译: 用于测量集成电路的至少两层之间的未对准的方法。 该方法包括在第一层中的多个探针构件之间施加电流,其中多个探针构件中的第一探针构件和第二探针构件沿着第一轴线基本上对准并且部分地与第二层中的覆盖目标重叠 测量所述多个探针构件上的电压,其中测量所述第一探针构件和垂直于所述第一轴线设置的至少一个电压以及横跨所述第二探针构件和所述第三探针构件的电压,并且确定 基于测量步骤沿着第一轴和第二轴的至少一个,第一层和第二层之间的未对准量。
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公开(公告)号:US20050095872A1
公开(公告)日:2005-05-05
申请号:US10605857
申请日:2003-10-31
IPC分类号: H01L21/314 , H01L21/316 , H01L21/318 , H01L21/762 , H01L21/8242 , H01L21/31 , H01L21/76
CPC分类号: H01L21/02164 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/31608 , H01L21/31625 , H01L21/31629 , H01L21/3185 , H01L21/76224 , H01L27/10844
摘要: An HDP process for high aspect ratio gap filling comprises contacting a semiconductor substrate with an oxide precursor under high density plasma conditions at a first pressure less than about 10 millitorr, wherein said gaps are partially filled with oxide; and further contacting the substrate with an oxide precursor under high density plasma conditions at a second pressure greater than about 10 millitorr, wherein said gaps are further filled with oxide.
摘要翻译: 用于高纵横比间隙填充的HDP工艺包括在高密度等离子体条件下以低于约10毫托的第一压力使半导体衬底与氧化物前体接触,其中所述间隙部分地填充有氧化物; 并且在高密度等离子体条件下,在大于约10毫托的第二压力下进一步使基底与氧化物前体接触,其中所述间隙进一步用氧化物填充。
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公开(公告)号:US06914015B2
公开(公告)日:2005-07-05
申请号:US10605857
申请日:2003-10-31
IPC分类号: H01L21/314 , H01L21/316 , H01L21/318 , H01L21/762 , H01L21/8242 , H01L21/31
CPC分类号: H01L21/02164 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/31608 , H01L21/31625 , H01L21/31629 , H01L21/3185 , H01L21/76224 , H01L27/10844
摘要: An HDP process for high aspect ratio gap filling comprises contacting a semiconductor substrate with an oxide precursor under high density plasma conditions at a first pressure less than about 10 millitorr, wherein said gaps are partially filled with oxide; and further contacting the substrate with an oxide precursor under high density plasma conditions at a second pressure greater than about 10 millitorr, wherein said gaps are further filled with oxide.
摘要翻译: 用于高纵横比间隙填充的HDP工艺包括在高密度等离子体条件下以低于约10毫托的第一压力使半导体衬底与氧化物前体接触,其中所述间隙部分地填充有氧化物; 并且在高密度等离子体条件下,在大于约10毫托的第二压力下进一步使基底与氧化物前体接触,其中所述间隙进一步用氧化物填充。
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