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公开(公告)号：US5774481A
公开(公告)日：1998-06-30
申请号：US414064
申请日：1995-03-31
CPC分类号： G06F11/1012 , H03M13/13
摘要： Error detection and correction circuitry, optimized to reduce the time required to correct single errors and to detect the presence of uncorrectable errors, uses an optimized H-Matrix and provides reduced logic circuitry. Correctable error syndromes are defined as comprising an odd number of ones and an uncorrectable-error detection circuit generates an uncorrectable-error indication when an even number of ones are detected. The correctable-error syndromes are defined as having a predefined combination of ones and zeros in each of a set of corresponding bit positions and different combinations of ones and zeros in other bit position. An error syndrome comprising only zeros is designated as indicative of a no error condition. Logic circuitry is provided which implements the error detection and correction circuitry with a reduced set of logic gates.
摘要翻译： 错误检测和校正电路，经过优化，可减少校正单个错误所需的时间并检测是否存在不可校正的错误，使用优化的H-Matrix并提供减少的逻辑电路。 可纠正的误差综合征被定义为包括奇数个，并且当检测到偶数个错误时，不可校正错误检测电路产生不可校正错误指示。 可校正错误综合征被定义为在一组相应位位置中的每一个中具有预定义的1和0的组合，以及在其它位位置中具有不同的1和0的组合。 仅包括零的错误综合征被指定为无错误状态的指示。 提供逻辑电路，其实现具有减少的逻辑门集合的错误检测和校正电路。
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公开(公告)号：US07627114B2
公开(公告)日：2009-12-01
申请号：US10263032
申请日：2002-10-02
申请人： Chin-Long Chen
发明人： Chin-Long Chen
IPC分类号： H04L9/00
摘要： Modular reduction and modular multiplication for large numbers are required operations in public key cryptography. Moreover, efficient execution of these two operations is important to achieve high performance levels in cryptographic engines and processes. The present invention uses multiplication and addition instead of using division and subtraction to perform modular arithmetic. The present invention also achieves some of its advantages through processing which begins with the high order bits coupled with judicious observations pertaining to circumstances under which carry output signals from addition operations are generated. These carry output signals are used to provide corrections which thus enable the use of the higher order bits and the efficiencies that such use engenders. Additionally, unlike other methods, the present invention avoids the baggage of preprocessing and post processing operations.
摘要翻译： 公钥加密中需要大量的模块化减法和模乘法。 此外，这两个操作的有效执行对于在加密引擎和进程中实现高性能水平很重要。 本发明使用乘法和加法而不是使用除法和执行模运算。 本发明还通过以高阶位开始的处理来实现其一些优点，其结合与生成来自加法运算的进位输出信号的情况有关的明智观察。 这些携带输出信号用于提供校正，从而使得能够使用更高级位和这种使用产生的效率。 此外，与其他方法不同，本发明避免了预处理和后处理操作的行李。
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3.发明授权公开(公告)号：US07093183B2
公开(公告)日：2006-08-15
申请号：US09795216
申请日：2001-02-28
申请人： Chin-Long Chen
发明人： Chin-Long Chen
IPC分类号： H03M3/00
CPC分类号： H03M13/134 , H03M13/6575
摘要： Error correction and detection codes are designed with several properties: the ability to perform error correction and detection operations via syndrome generation in multiple cycles of information delivery from a source such as a set of memory chips; a code structure which is cooperatively designed in terms of the bits-per-chip architecture of a set of memory chips so as to provide enhanced robustness in the face of bus line and chip failures; and a structured parity check matrix which provides circuits which are cheaper, take up less room, and are faster than standard designs.
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公开(公告)号：US06963977B2
公开(公告)日：2005-11-08
申请号：US09740411
申请日：2000-12-19
申请人： Chin-Long Chen , Edward W. Chencinski , Vincenzo Condorelli , Leonard L. Fogell , Samir K. Patel
发明人： Chin-Long Chen , Edward W. Chencinski , Vincenzo Condorelli , Leonard L. Fogell , Samir K. Patel
CPC分类号： G06F7/723
摘要： The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to circuits and methods for carrying out modular exponentiation.
摘要翻译： 在公开密钥加密和解密系统中使用的模幂运算功能是在独立的引擎中实现的，该独立引擎在其核心模乘法电路中分两个阶段工作，这两个阶段共享重叠的硬件结构。 将硬件结构中的大阵列用于乘法和加法分割成更小的结构导致乘法器设计，其包括以链式方式链接在一起的一系列几乎相同的处理元件。 作为分段处理元件的两相操作和链接在一起的结果，整体结构以流水线方式操作以提高生产量和速度。 链式处理元件被构造成提供具有用于处理模量因子的单独部件的可分隔链。 在这种模式下，该系统特别适用于利用中国剩余定理的特征进行快速求幂运算。 还提供校验和机制以确保精确的操作而不影响速度并且不会显着增加复杂性。 虽然本公开涉及包括许多特征的复杂系统，但是本申请特别涉及用于执行模幂运算的电路和方法。
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公开(公告)号：US20050188209A1
公开(公告)日：2005-08-25
申请号：US09740411
申请日：2000-12-19
CPC分类号： G06F7/723
摘要： The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to circuits and methods for carrying out modular exponentiation.
摘要翻译： 在公开密钥加密和解密系统中使用的模幂运算功能是在独立的引擎中实现的，该独立引擎在其核心模乘法电路中分两个阶段工作，这两个阶段共享重叠的硬件结构。 将硬件结构中的大阵列用于乘法和加法分割成更小的结构导致乘法器设计，其包括以链式方式链接在一起的一系列几乎相同的处理元件。 作为分段处理元件的两相操作和链接在一起的结果，整体结构以流水线方式操作以提高生产量和速度。 链式处理元件被构造成提供具有用于处理模量因子的单独部件的可分隔链。 在这种模式下，该系统特别适用于利用中国剩余定理的特征进行快速求幂运算。 还提供校验和机制以确保精确的操作而不影响速度并且不会显着增加复杂性。 虽然本公开涉及包括许多特征的复杂系统，但是本申请特别涉及用于执行模幂运算的电路和方法。
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公开(公告)号：US06519736B1
公开(公告)日：2003-02-11
申请号：US09452079
申请日：1999-11-30
IPC分类号： G11C2900
CPC分类号： H03M13/11 , G06F11/1008 , H03M13/19
摘要： Uncorrectable errors are isolated to one component of a computing system comprising a plurality of components. First, upon detection of an uncorrectable error, a special check bit pattern is generated. This check bit pattern is used to indicate the occurrence of an uncorrectable error, as well as the location of the occurrence of the error. Subsequently, the check bit pattern is incorporated into the data word being transmitted, and thus may be used to isolate an uncorrectable error to the exact location of occurrence.
摘要翻译： 不可纠正的错误被隔离到包括多个组件的计算系统的一个组件。 首先，当检测到不可校正的错误时，产生特殊的校验位模式。 该检查位模式用于指示出现不可校正错误以及发生错误的位置。 随后，校验位模式被合并到被发送的数据字中，因此可以用于将不可校正的误差隔离到确切的发生位置。
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7.发明授权Single symbol correction double symbol detection code employing a modular H-matrix 有权采用模块化H矩阵的单符号校正双符号检测码公开(公告)号：US06463563B1
公开(公告)日：2002-10-08
申请号：US09451133
申请日：1999-11-30
IPC分类号： G11C2900
CPC分类号： G11C29/02
摘要： An error correction code for single symbol error correction and double symbol error detection is generated according to a novel modular H-matrix. The H-matrix utilizes a modular design with multiple iterations of a plurality of subsets. In particular, one example of this H-matrix includes a plurality of rows and columns with each of at least one row of the H-matrix comprising, in part, multiple iterations of one subset of the plurality of subsets. The remainder of the rows, comprises, in part, a cyclic permutation of all of the remaining subsets of the plurality of subsets.
摘要翻译： 根据新型模块化H矩阵生成单符号纠错和双符号错误检测的纠错码。 H矩阵利用具有多个子集的多次迭代的模块化设计。 特别地，该H矩阵的一个示例包括多个行和列，其中H矩阵的至少一行中的每一行部分地包括多个子集中的一个子集的多次迭代。 行的其余部分部分地包括多个子集中的所有剩余子集的循环排列。
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公开(公告)号：US06392571B1
公开(公告)日：2002-05-21
申请号：US09852893
申请日：2001-05-10
IPC分类号： H03M700
CPC分类号： H03M7/30
摘要： The present invention employs an extra array of character history matching storage flip flops wherein the extra set operates in an alternating sequence with the first set depending upon the occurrence of a character mismatch, to ensure that every character received by a data compressing system is treated and considered in the same clock cycle in which it is received. The resultant circuit and method provides a much more speedy and efficient method for compressing data and for preprocessing of data which is to be compressed.
摘要翻译： 本发明采用与存储触发器相匹配的字符历史的额外数组，其中额外集合以取决于字符不匹配的出现的第一集合的交替序列操作，以确保处理由数据压缩系统接收的每个字符， 在接收它的同一个时钟周期内考虑。 所得到的电路和方法提供了一种更加快速和有效的压缩数据和预处理要压缩的数据的方法。
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公开(公告)号：US6009548A
公开(公告)日：1999-12-28
申请号：US23969
申请日：1998-06-18
申请人： Chin-Long Chen , Timothy Jay Dell , Wayne C. Kwan
发明人： Chin-Long Chen , Timothy Jay Dell , Wayne C. Kwan
CPC分类号： G06F11/1012 , H03M13/151 , G06F11/1028
摘要： A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip. The invention provides 84/72 ECC for computer systems having a four bit per chip memory configuration and 88/72 ECC for computer systems having an eight bit per chip memory configuration. Further embodiments describe the detection and communication of uncorrectable errors.
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公开(公告)号：US5425038A
公开(公告)日：1995-06-13
申请号：US87442
申请日：1993-07-02
申请人： Chin-Long Chen
发明人： Chin-Long Chen
CPC分类号： G06F11/1028 , G06F11/10 , H03M13/15
摘要： In accordance with a preferred embodiment of the present invention, a mechanism is provided for converting Type II binary parity check matrices for a large class of codes into a larger parity check matrix which is more suitable for error detection and correction in memory systems which employ multiple bit per chip output architecture. More particularly, the present coding method provides codes which exhibit check bit requirements which are less than those for a Type II code but greater than those for a Type I code. In particular, the codes of the present invention are capable of detecting all combinations of a single symbol error and a single bit error. In addition, the codes for the present invention exhibit all of the correction and detection properties for a Type I code but do not rise to the capabilities or the complexities of Type II codes which are capable of correcting all single symbol errors and detecting all double symbol errors. In particular, the present invention avoids the weakness found a in Type I code which occurs in those situations in which there is a symbol error from a symbol bit group and another error from a different symbol.
摘要翻译： 根据本发明的优选实施例，提供了一种用于将用于大类代码的II型二进制奇偶校验矩阵转换为更大的奇偶校验矩阵的机制，其更适合于采用多个的存储器系统中的错误检测和校正 每芯片输出架构。 更具体地说，本编码方法提供了代表类型II代码但是大于类型I代码的检验比特要求的代码。 特别地，本发明的代码能够检测单个符号错误和单个位错误的所有组合。 另外，本发明的代码表现出对于类型I代码的所有校正和检测属性，但不会升高到能够校正所有单个符号错误并检测所有双符号的II型代码的能力或复杂性 错误。 特别地，本发明避免了发生在从符号位组出现符号错误和来自不同符号的另一错误的那些情况下出现的I型代码中的弱点。
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