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    Semiconductor chip having both compact memory and high performance logic
    1.
    发明授权
    Semiconductor chip having both compact memory and high performance logic 有权
    具有紧凑型存储器和高性能逻辑的半导体芯片

    公开(公告)号：US06686617B2

    公开(公告)日：2004-02-03

    申请号：US09878804

    申请日：2001-06-11

    申请人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

    发明人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

    IPC分类号： H01L27108

    CPC分类号： H01L27/10861 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/10873 ,  H01L27/10894

    摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

    摘要翻译： 在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。 该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件 逻辑区域。 将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。 然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。 还公开了由该方法的各种实施方案产生的芯片结构。

    Double polysilicon process for providing single chip high performance logic and compact embedded memory structure
    2.
    发明授权
    Double polysilicon process for providing single chip high performance logic and compact embedded memory structure 有权
    双晶硅工艺，提供单芯片高性能逻辑和紧凑型嵌入式存储器结构

    公开(公告)号：US06287913B1

    公开(公告)日：2001-09-11

    申请号：US09427506

    申请日：1999-10-26

    申请人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

    发明人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

    IPC分类号： H01L218242

    CPC分类号： H01L27/10861 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/10873 ,  H01L27/10894

    摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

    摘要翻译： 在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。 该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件 逻辑区域。 将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。 然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。 还公开了由该方法的各种实施方案产生的芯片结构。

    Circuit and methods of adaptive charge-pump regulation
    3.
    发明授权
    Circuit and methods of adaptive charge-pump regulation 有权
    自适应电荷泵调节的电路和方法

    公开(公告)号：US07944277B1

    公开(公告)日：2011-05-17

    申请号：US12340076

    申请日：2008-12-19

    申请人： Dennis Sinitsky ,  Shafiq M. Jamal

    发明人： Dennis Sinitsky ,  Shafiq M. Jamal

    IPC分类号： G05F1/10

    CPC分类号： G05F1/56 ,  H02M3/07

    摘要： In one embodiment, the present invention includes a circuit for suppressing noise with adaptive charge-pump regulation. The circuit comprises an oscillator circuit, a charge pump, an amplifier, a current mirror, and a filter. The charge-pump receives an oscillating signal and provides an output voltage. The amplifier is responsive to the output voltage and a reference voltage and provides a control signal. The control signal alters a frequency of the oscillator and the output voltage is responsive to this frequency. The current mirror and filter suppress a noise component of the output voltage. The current mirror provides a supply current to a regulator loop. The regulator loop is operable to generate a consistent regulator voltage. In this manner, the adaptive charge-pump allows for a more consistent, noise free, regulator voltage.

    摘要翻译： 在一个实施例中，本发明包括用于利用自适应电荷泵调节来抑制噪声的电路。 电路包括振荡电路，电荷泵，放大器，电流镜和滤波器。 电荷泵接收振荡信号并提供输出电压。 放大器响应于输出电压和参考电压，并提供控制信号。 控制信号改变振荡器的频率，并且输出电压响应于该频率。 电流镜和滤波器抑制输出电压的噪声分量。 电流镜向调节器回路提供电源电流。 调节器环路可操作以产生一致的调节器电压。 以这种方式，自适应电荷泵允许更一致，无噪声的调节器电压。

    Non-Volatile Memory In CMOS Logic Process
    5.
    发明申请
    Non-Volatile Memory In CMOS Logic Process 审中-公开
    CMOS逻辑过程中的非易失性存储器

    公开(公告)号：US20080151623A1

    公开(公告)日：2008-06-26

    申请号：US12045593

    申请日：2008-03-10

    申请人： Gang-feng Fang ,  Dennis Sinitsky ,  Wingyu Leung

    发明人： Gang-feng Fang ,  Dennis Sinitsky ,  Wingyu Leung

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).

    摘要翻译： 一种方法，装置和系统，其中根据常规逻辑处理器制造的嵌入式存储器包括一个或多个电可更改的非易失性存储单元，每个具有编程晶体管，读取晶体管和控制电容器，其共享一个 普通浮栅电极。 编程晶体管和控制电容器的源极/漏极区域的不足扩散最大化。 在一个实施例中，编程晶体管的源极/漏极区域通过晶体管穿通（或直接接触）电触发。

    Class-AB XTAL circuit
    6.
    发明授权
    Class-AB XTAL circuit 失效
    AB类XTAL电路

    公开(公告)号：US08704605B1

    公开(公告)日：2014-04-22

    申请号：US13353852

    申请日：2012-01-19

    申请人： Dennis Sinitsky ,  Junshi Qiao ,  Shafiq M. Jamal ,  Tao Shui

    发明人： Dennis Sinitsky ,  Junshi Qiao ,  Shafiq M. Jamal ,  Tao Shui

    IPC分类号： H03B5/36

    CPC分类号： H03B5/364 ,  H03B5/36 ,  H03B5/362 ,  H03B2200/0012 ,  H03B2200/0062

    摘要： A resonant element driver circuit includes a NMOS transistor and a PMOS transistor that are configured to drive a resonant element. The resonant element driver circuit includes biasing circuitry that is configured to bias the PMOS transistor. The biasing circuitry receives a reference signal that is used to set the biasing on the PMOS transistor. The resonant element driver further includes mirror circuitry that tracks current flowing through the NMOS and PMOS transistors.

    摘要翻译： 谐振元件驱动电路包括被配置为驱动谐振元件的NMOS晶体管和PMOS晶体管。 谐振元件驱动电路包括被配置为偏置PMOS晶体管的偏置电路。 偏置电路接收用于设置PMOS晶体管上的偏置的参考信号。 谐振元件驱动器还包括跟踪流过NMOS和PMOS晶体管的电流的反射镜电路。

    Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process
    7.
    发明申请
    Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process 审中-公开
    增加在单门逻辑过程中制造的非易失性存储器的电荷保留的方法

    公开(公告)号：US20070170489A1

    公开(公告)日：2007-07-26

    申请号：US11341881

    申请日：2006-01-26

    申请人： Gang-feng Fang ,  Dennis Sinitsky ,  Wingyu Leung

    发明人： Gang-feng Fang ,  Dennis Sinitsky ,  Wingyu Leung

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42324

    摘要： A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

    摘要翻译： 具有增加的电荷保持的非易失性存储单元使用单栅极常规逻辑工艺在与逻辑器件相同的衬底上制造。 在NVM单元的浮动栅极上形成硅化物阻挡介质结构，从而防止在浮栅上形成硅化物，同时允许在逻辑器件上形成硅化物。 在NVM电池中防止硅化物尖峰和桥接，因为硅化物阻挡电介质结构防止硅化物金属与浮动栅极或相邻的侧壁间隔物接触。 硅化物阻挡电介质层可以暴露NVM电池的有源区的部分，远离浮动栅极和相邻的侧壁间隔物，从而使得这些部分上形成硅化物。 或者，硅化物阻挡电介质层可以在硅化物形成期间覆盖NVM电池的有源区。 在这种情况下，硅化物阻挡介电层可以在形成硅化物之后变薄或去除。

    Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process
    8.
    发明授权
    Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process 有权
    增加在单门逻辑过程中制造的非易失性存储器的电荷保留的方法

    公开(公告)号：US07919367B2

    公开(公告)日：2011-04-05

    申请号：US12021229

    申请日：2008-01-28

    申请人： Gang-feng Fang ,  Dennis Sinitsky ,  Wingyu Leung

    发明人： Gang-feng Fang ,  Dennis Sinitsky ,  Wingyu Leung

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

    摘要翻译： 具有增加的电荷保持的非易失性存储单元使用单栅极常规逻辑工艺在与逻辑器件相同的衬底上制造。 在NVM单元的浮动栅极上形成硅化物阻挡介质结构，从而防止在浮栅上形成硅化物，同时允许在逻辑器件上形成硅化物。 在NVM电池中防止硅化物尖峰和桥接，因为硅化物阻挡电介质结构防止硅化物金属与浮动栅极或相邻的侧壁间隔物接触。 硅化物阻挡电介质层可以暴露NVM电池的有源区的部分，远离浮动栅极和相邻的侧壁间隔物，从而使得这些部分上形成硅化物。 或者，硅化物阻挡电介质层可以在硅化物形成期间覆盖NVM电池的有源区。 在这种情况下，硅化物阻挡介质层可以在形成硅化物之后变薄或去除。

    Non-volatile memory in CMOS logic process
    9.
    发明授权
    Non-volatile memory in CMOS logic process 有权
    CMOS逻辑过程中的非易失性存储器

    公开(公告)号：US07671401B2

    公开(公告)日：2010-03-02

    申请号：US11262141

    申请日：2005-10-28

    申请人： Gang-feng Fang ,  Dennis Sinitsky ,  Wingyu Leung

    发明人： Gang-feng Fang ,  Dennis Sinitsky ,  Wingyu Leung

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).

    摘要翻译： 一种方法，装置和系统，其中根据常规逻辑处理器制造的嵌入式存储器包括一个或多个电可更改的非易失性存储单元，每个具有编程晶体管，读取晶体管和控制电容器，其共享一个 普通浮栅电极。 编程晶体管和控制电容器的源极/漏极区域的不足扩散最大化。 在一个实施例中，编程晶体管的源极/漏极区域通过晶体管穿通（或直接接触）电触发。

    Low power relaxation oscillator
    10.
    发明授权
    Low power relaxation oscillator 有权
    低功率弛豫振荡器

    公开(公告)号：US09048821B2

    公开(公告)日：2015-06-02

    申请号：US13923297

    申请日：2013-06-20

    申请人： Dennis Sinitsky ,  Praveen Kallam

    发明人： Dennis Sinitsky ,  Praveen Kallam

    IPC分类号： H03K3/02 ,  H03K3/0231

    CPC分类号： H03K3/0231

    摘要： A relaxation oscillator circuit includes a comparator including a first input, a second input, a bias input, and an output. The first input is coupled to a charging node, and the second input is configured to receive a reference voltage. The relaxation oscillator circuit further includes a first bias circuit configured to provide a bias signal to the bias input of the first comparator when a first node voltage on the charging node exceeds a first reference.

    摘要翻译： 松弛振荡器电路包括比较器，包括第一输入端，第二输入端，偏置输入端和输出端。 第一输入耦合到充电节点，并且第二输入被配置为接收参考电压。 张弛振荡器电路还包括第一偏置电路，其被配置为当充电节点上的第一节点电压超过第一参考时，向第一比较器的偏置输入提供偏置信号。