公开(公告)号：US6101557A

公开(公告)日：2000-08-08

申请号：US87637

申请日：1998-05-29

申请人： Paul Edward Movall ,  Charles Scott Graham ,  Shawn M. Lambeth ,  Daniel Frank Moertl

发明人： Paul Edward Movall ,  Charles Scott Graham ,  Shawn M. Lambeth ,  Daniel Frank Moertl

IPC分类号： G06F13/14 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4068

摘要： A method, device and system for configuring multifunction I/O device adapters connected to a bus utilizes a slot owner configuration register to identify the ownership of each function slot within the multi-function I/O device adapter. An intelligent I/O device adapter or controller within the multi-function I/O device adapter may control other I/O adapters located in other function slots through the information provided in the slot owner configuration register. Ownership of each slot is initially set, upon power up, to the host unit or processor complex. Thereafter, each intelligent I/O device adapter or controller determines the presence of adapters at other function slots to be controlled, and records this information in the slot owner configuration register.

摘要翻译： 用于配置连接到总线的多功能I / O设备适配器的方法，设备和系统利用插槽所有者配置寄存器来识别多功能I / O设备适配器内的每个功能插槽的所有权。 多功能I / O设备适配器中的智能I / O设备适配器或控制器可以通过插槽所有者配置寄存器中提供的信息来控制位于其他功能插槽中的其他I / O适配器。 每个插槽的所有权在上电时初始设置为主机单元或处理器组合。 此后，每个智能I / O设备适配器或控制器确定在要控制的其他功能插槽中存在适配器，并将该信息记录在插槽所有者配置寄存器中。

公开(公告)号：US6085277A

公开(公告)日：2000-07-04

申请号：US950755

申请日：1997-10-15

申请人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  William Joseph Armstrong ,  Thomas Rembert Sand

发明人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  William Joseph Armstrong ,  Thomas Rembert Sand

IPC分类号： G06F9/46 ,  G06F13/00

CPC分类号： G06F9/546

摘要： An interrupt and message batching apparatus and method reduces the number and frequency of processor interrupts and resulting context switches by grouping I/O completion events together with a single processor interrupt in a manner that balances I/O operation latency requirements with processor utilization requirements to optimize overall computer system performance. The invention sends a message from a processor complex to an I/O adapter on an I/O bus commanding an I/O device connected to the I/O adapter to perform a function. Upon completion of the commanded function, the message processor in the I/O adapter generates a message and sends it to the processor complex on the I/O bus. The message is enqueued in the message queue of the memory, a message count is updated, and processor complex interrupt is signalled if and when the message count exceeds a message pacing count. A signalling timer may also be programmed with a fast response time value if the message has a relatively high latency or with a slow response time value if the message has a relatively low latency. The signalling timer is started when the message is enqueued and the processor complex interrupt is then signalled when the message count exceeds the message pacing count or when the signalling timer has elapsed.

摘要翻译： 中断和消息批处理设备和方法通过将I / O完成事件与单个处理器中断分组，以使I / O操作等待时间要求与处理器利用率要求平衡来优化，从而减少处理器中断和结果上下文切换的数量和频率 整体计算机系统性能。 本发明在I / O总线上从处理器复合体向I / O适配器发送消息，命令连接到I / O适配器的I / O设备执行功能。 完成命令功能后，I / O适配器中的消息处理器会生成一条消息，并将其发送到I / O总线上的处理器复合体。 该消息在存储器的消息队列中排队，消息计数被更新，并且当消息计数超过消息步调计数时以及何时发送处理器复杂中断。 如果消息具有相对较高的延迟，或者如果消息具有相对低的延迟，则信令定时器也可以被编程为具有快速的响应时间值。 当消息排入队列时，启动信令定时器，然后当消息计数超过消息起搏计数或信令定时器过去时，信号通知处理器复杂中断。

公开(公告)号：US6023736A

公开(公告)日：2000-02-08

申请号：US995157

申请日：1997-12-19

申请人： Shawn Michael Lambeth ,  Charles Scott Graham ,  Daniel Frank Moertl ,  Paul Edward Movall ,  Gregory Michael Nordstrom

发明人： Shawn Michael Lambeth ,  Charles Scott Graham ,  Daniel Frank Moertl ,  Paul Edward Movall ,  Gregory Michael Nordstrom

IPC分类号： G06F13/10

CPC分类号： G06F13/102

摘要： An apparatus, system and method permitting dynamic configuration of I/O device adapters connected to a bus utilizes a function configuration register to store a READY/NOT READY status for each of the I/O device adapters. Upon the occurrence of a reset condition, dynamic configuration decision logic detects which I/O device adapters are connected to the bus, determines configuration parameters for each connected I/O device adapter, initializes the configuration space for each connected I/O device adapter, and then sets a corresponding flag in the function configuration register to indicate ready status. An I/O device driver interrupts a configuration process to examine the function configuration register. If ready status can be confirmed from this function configuration register within a time out period, then the configuration process may proceed; otherwise, a device error recovery process is initiated.

摘要翻译： 允许动态配置连接到总线的I / O设备适配器的设备，系统和方法利用功能配置寄存器来存储每个I / O设备适配器的READY / NOT READY状态。 在发生复位条件时，动态配置决策逻辑检测哪个I / O设备适配器连接到总线，确定每个连接的I / O设备适配器的配置参数，初始化每个连接的I / O设备适配器的配置空间， 然后在功能配置寄存器中设置相应的标志，以指示就绪状态。 I / O设备驱动程序中断配置过程以检查功能配置寄存器。 如果可以在超时期内从该功能配置寄存器确认就绪状态，则可以进行配置处理; 否则，启动设备错误恢复过程。

公开(公告)号：US5983292A

公开(公告)日：1999-11-09

申请号：US950593

申请日：1997-10-15

申请人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  Thomas Rembert Sand

发明人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  Thomas Rembert Sand

IPC分类号： G06F13/12 ,  G06F13/10 ,  G06F13/14

CPC分类号： G06F13/126

摘要： An I/O system including a processor complex and system main memory connected to I/O adapters via I/O adapters and I/O bus. A message transport mechanism and method stores an upstream message queue and a downstream message queue in system main memory. Queue addresses are stored both in system main memory and designated registers of I/O adapters. The I/O adapters utilize the queue addresses to manage the transfer of downstream command messages and to send upstream response messages to the system main memory via direct memory access across the I/O bus.

摘要翻译： 一个I / O系统，包括一个处理器复合体和通过I / O适配器和I / O总线连接到I / O适配器的系统主存储器。 消息传送机制和方法将上游消息队列和下游消息队列存储在系统主存储器中。 队列地址存储在系统主存储器和I / O适配器的指定寄存器中。 I / O适配器利用队列地址来管理下游命令消息的传输，并通过跨I / O总线的直接存储器访问将上行响应消息发送到系统主存储器。

公开(公告)号：US06721839B1

公开(公告)日：2004-04-13

申请号：US09748983

申请日：2000-12-27

申请人： Ellen Marie Bauman ,  David Lee Dosch ,  Charles Scott Graham ,  Brian Gerard Holthaus ,  Daniel Robert Lipps ,  Daniel Frank Moertl ,  Paul Edward Movall ,  Daniel Paul Wetzel

发明人： Ellen Marie Bauman ,  David Lee Dosch ,  Charles Scott Graham ,  Brian Gerard Holthaus ,  Daniel Robert Lipps ,  Daniel Frank Moertl ,  Paul Edward Movall ,  Daniel Paul Wetzel

IPC分类号： G06F1300

CPC分类号： G06F13/404

摘要： A method and apparatus are provided for mapping multiple address spaces into a single bus, such as a single peripheral component interconnect (PCI) bus. The single bus is coupled to a first processor complex and a second processor complex. An original address of a memory access is shifted to a unique address space for each originator/target of an operation. The shifted address is used on the single bus. Then the shifted address is shifted back to the original address for completing the operation on a destination bus. The original address of a memory access is shifted to a unique address space for each originator/target of an operation using a respective predefined value (+X1, +X2, or +X3) for shifting the original address above a predefined boundary for each originator/target of the operation. Shifting back the shifted address to the original address for completing the operation on the destination bus uses a respective predefined value (−X1, −X2, or −X3) for the shifted back address to the original address for completing the operation on the destination bus. Using the shifted address on the single bus utilizes a dual address cycle (DAC) of the single bus for the shifted address. Completing the operation on a destination bus utilizes a single address cycle (SAC) of the destination bus for the shifted back address to the original address.

摘要翻译： 提供了一种用于将多个地址空间映射到单个总线（诸如单个外围组件互连（PCI）总线）的方法和装置。 单总线耦合到第一处理器复合体和第二处理器复合体。 存储器访问的原始地址被移动到操作的每个发起者/目标的唯一地址空间。 移位的地址用于单总线。 然后将移位的地址移回原始地址，以完成目标总线上的操作。 使用相应的预定义值（+ X1，+ X2或+ X3）将存储器访问的原始地址移动到每个发起者/目标的唯一地址空间，用于将原始地址移动到每个发起者的预定边界之上 /目标的操作。 将移动的地址移动到原始地址以完成目的地总线上的操作，将移位后地址的相应预定义值（-X1，-X2或-X3）用于原始地址，以完成目标总线上的操作 。 使用单总线上的移位地址，可以使用单总线的双地址周期（DAC）作为移位地址。 在目的地总线上完成操作将目的地总线的单个地址周期（SAC）用于移位后地址到原始地址。

公开(公告)号：US06219761B1

公开(公告)日：2001-04-17

申请号：US09072740

申请日：1998-05-06

申请人： Paul Edward Movall ,  Charles Scott Graham ,  Shawn Michael Lambeth ,  Daniel Frank Moertl

发明人： Paul Edward Movall ,  Charles Scott Graham ,  Shawn Michael Lambeth ,  Daniel Frank Moertl

IPC分类号： G06F1328

CPC分类号： G06F13/126 ,  G06F9/3879

摘要： An input/output bus architecture that includes: an input/output bus; an input/output device connected to the input/output bus; a main processor, connected to the input/output bus, for executing a device driver corresponding to the input/output device, the device driver generating load/store commands for the input/output device; and a load/store assist engine, connected to the input/output bus and yet independent of the main processor, for loading/storing data to/from the input/output device according to the load/store commands from the device driver. The load/store assist engine decouples the main processor from latencies associated with execution of the load/store commands. The device driver is reassigned to the main processor, rather than being found in a device that is external to the main processor, such as an input/output processor.

摘要翻译： 输入/输出总线架构，包括：输入/输出总线; 连接到输入/输出总线的输入/输出设备; 连接到输入/输出总线的主处理器，用于执行与输入/输出设备相对应的设备驱动器，设备驱动器为输入/输出设备产生加载/存储命令; 以及负载/存储辅助引擎，其连接到输入/输出总线，并且独立于主处理器，用于根据来自设备驱动程序的加载/存储命令向/从输入/输出设备加载/存储数据。 加载/存储辅助引擎将主处理器与与执行加载/存储命令相关联的延迟分离。 设备驱动程序被重新分配给主处理器，而不是在主处理器外部的设备（例如输入/输出处理器）中找到。

公开(公告)号：US06233641B1

公开(公告)日：2001-05-15

申请号：US09093441

申请日：1998-06-08

申请人： Charles Scott Graham ,  Shawn Michael Lambeth ,  Daniel Frank Moertl ,  Paul Edward Movall

发明人： Charles Scott Graham ,  Shawn Michael Lambeth ,  Daniel Frank Moertl ,  Paul Edward Movall

IPC分类号： G06F1338

CPC分类号： G06F13/4022 ,  G06F13/4045

摘要： A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.

摘要翻译： PCI扩展卡接口的主PCI总线和多个辅助PCI总线通过路由电路互连。 路由电路通过将每个辅助PCI总线与地址范围相关联并将从主PCI总线接收的命令转发到辅助PCI总线映射，分别用作主PCI总线和每个辅助PCI总线之间的交换桥 到包括命令地址的地址范围。 此外，路由电路从辅助PCI总线转发用于主PCI总线的命令。 此外，当从一个辅助PCI总线接收的命令用于另一个PCI总线时，路由电路直接在辅助PCI总线之间路由命令，而不使用主总线。 因此，主PCI总线上的流量和延迟降低，效率提高。

公开(公告)号：US6073253A

公开(公告)日：2000-06-06

申请号：US995075

申请日：1997-12-19

申请人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  Paul John Johnsen ,  Thomas Rembert Sand

发明人： Gregory Michael Nordstrom ,  Shawn Michael Lambeth ,  Paul Edward Movall ,  Daniel Frank Moertl ,  Charles Scott Graham ,  Paul John Johnsen ,  Thomas Rembert Sand

IPC分类号： G06F1/24 ,  G06F11/267 ,  G06F11/00

CPC分类号： G06F11/267 ,  G06F1/24

摘要： An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state. Each of these reset states is well-defined and has the advantage of predictable behavior during and after execution of the corresponding reset procedure. A built-in self-test procedure is also defined that sequentially examines each function associated within a multifunction device connected to the local bus to coordinate the initiation, execution and completion of built in self-tests.

摘要翻译： 允许各种复位过程和相应复位状态的装置，系统和方法。 为单个功能或多功能设备中的每个I / O设备适配器提供器件复位控制寄存器。 器件复位控制寄存器允许对单个功能器件，多功能器件作为一个整体进行更大程度的控制，以及多功能器件中的各个器件功能。 设备立即状态寄存器可以同步各种复位过程。 逻辑上电复位程序，有向单元复位程序和定向接口复位程序利用设备复位控制寄存器提供的更大程度的控制力将I / O设备适配器，单功能设备或多功能设备强制为相应的逻辑 上电复位状态，定向单元复位状态或定向接口复位状态。 这些复位状态中的每一个都被明确定义，并且具有在执行相应的复位过程期间和之后可预测的行为的优点。 还定义了一个内置的自检程序，依次检查连接到本地总线的多功能设备中相关联的每个功能，以协调内置自检的启动，执行和完成。

公开(公告)号：US07225364B2

公开(公告)日：2007-05-29

申请号：US10388071

申请日：2003-03-13

申请人： Michael Joseph Carnevale ,  Charles Scott Graham ,  Daniel Frank Moertl ,  Timothy Jerry Schimke

发明人： Michael Joseph Carnevale ,  Charles Scott Graham ,  Daniel Frank Moertl ,  Timothy Jerry Schimke

IPC分类号： G06F11/00

CPC分类号： G06F13/12

摘要： A method, apparatus, and computer program product are provided for implementing a receive function over an interconnect network, such as InfiniBand. A virtual lane (VL) with a pending packet for a queue pair (QP) is selected. Then the pending packet is checked for an exceptional condition. Responsive to identifying the exceptional condition for the pending packet, a state bit is set for freezing the selected VL; and an interrupt is generated to firmware. Responsive to receiving the interrupt, the firmware determines a cause for freezing the selected VL and performs a responsive action. For example, the responsive action performed by firmware includes firmware performing an error recovery procedure (ERP) for the QP; firmware updating a state for the QP; or firmware performing application unique processing for the QP.

摘要翻译： 提供了一种用于通过诸如InfiniBand的互连网络实现接收功能的方法，装置和计算机程序产品。 选择具有用于队列对（QP）的等待分组的虚拟通道（VL）。 然后检查待处理的数据包是否有特殊情况。 响应于识别待处理分组的异常情况，设置状态位以冻结所选择的VL; 并向固件生成中断。 响应于接收中断，固件确定冻结所选VL的原因并执行响应动作。 例如，由固件执行的响应动作包括执行QP的错误恢复过程（ERP）的固件; 固件更新QP的状态; 或执行针对QP的应用唯一处理的固件。

公开(公告)号：US07212547B2

公开(公告)日：2007-05-01

申请号：US10360252

申请日：2003-02-06

申请人： Michael Joseph Carnevale ,  Charles Scott Graham ,  Daniel Frank Moertl ,  Timothy Jerry Schimke

发明人： Michael Joseph Carnevale ,  Charles Scott Graham ,  Daniel Frank Moertl ,  Timothy Jerry Schimke

IPC分类号： H04J3/16 ,  H04J3/22

CPC分类号： H04L49/90

摘要： A method, apparatus, and computer program product are provided for implementing global to local queue pair translation in a network transport layer. A global queue pair number is identified. The global queue pair number is translated to a smaller local queue pair number. The local queue pair number is used for storing local queue pair context data for outbound header generation and inbound header checking. Upper layers of the network protocol above the network transport layer are allowed to use the global queue pair numbers.

摘要翻译： 提供了一种用于在网络传输层中实现全局到本地队列对转换的方法，装置和计算机程序产品。 识别全局队列对号码。 全局队列对号被转换为较小的本地队列对。 本地队列对号用于存储用于出站报头生成和入站报头检查的本地队列对上下文数据。 允许网络传输层上方网络协议的上层使用全局队列对。