公开(公告)号：US07185306B1

公开(公告)日：2007-02-27

申请号：US10915647

申请日：2004-08-09

申请人： Paul Leventis ,  David Cashman

发明人： Paul Leventis ,  David Cashman

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method for enhancing signal routability within an integrated circuit is provided. The method initiates with examining an outer edge of a sequence of logical array blocks. The method includes identifying an undriven routing wire in a vicinity of the outer edge. An underutilized driver proximate to the undriven routing wire is also identified. Then, the underutilized driver is coupled to the undriven routing wire. A computer readable medium and an integrated circuit are also provided.

摘要翻译： 提供了一种用于增强集成电路内的信号可路由性的方法。 该方法通过检查逻辑阵列块序列的外边缘来启动。 该方法包括识别外边缘附近的未驱动布线。 还识别了靠近未驱动路线的未充分利用的驾驶员。 然后，未充分利用的驱动器耦合到未驱动的布线。 还提供了计算机可读介质和集成电路。

公开(公告)号：US06965249B2

公开(公告)日：2005-11-15

申请号：US10159581

申请日：2002-05-30

申请人： Christopher Lane ,  Ketan Zaveri ,  Hyun Yi ,  Giles Powell ,  Paul Leventis ,  David Jefferson ,  David Lewis ,  Triet Nguyen ,  Vikram Santurkar ,  Michael Chan ,  Andy Lee ,  Brian Johnson ,  David Cashman

发明人： Christopher Lane ,  Ketan Zaveri ,  Hyun Yi ,  Giles Powell ,  Paul Leventis ,  David Jefferson ,  David Lewis ,  Triet Nguyen ,  Vikram Santurkar ,  Michael Chan ,  Andy Lee ,  Brian Johnson ,  David Cashman

IPC分类号： H01L21/82 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/17736 ,  H03K19/17744

摘要： A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

摘要翻译： 可编程逻辑器件和相关方法提供有可修复区域。 在一个方面，一般布线互连线在可修复区域内被分段。 在另一方面，提供IO总线线路和相关电路，其适应交错分段结构中的冗余。 在另一方面，特定逻辑区域之间的专用路由架构适应移位以限定和利用可修复区域。 在本发明的方面的几个示例性实施例的上下文中示出和描述了其它方面的原理。

公开(公告)号：US20120112791A1

公开(公告)日：2012-05-10

申请号：US13347626

申请日：2012-01-10

申请人： David Lewis ,  David Cashman ,  Jeffery Christopher Chromczack

发明人： David Lewis ,  David Cashman ,  Jeffery Christopher Chromczack

IPC分类号： H03K19/096

CPC分类号： H03K3/0375

摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器显示出通过条件降低的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。

公开(公告)号：US20080218208A1

公开(公告)日：2008-09-11

申请号：US11684424

申请日：2007-03-09

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/177

CPC分类号： H03K19/17736

摘要： A PLD with LAB interconnect lines that span adjacent LABs in the array and that have the ability to interconnect two logic elements in the different LABs. The PLD includes a plurality of LABs arranged in an array and a plurality of inter-LAB lines interconnecting the LABs of the array. Each of the LABs include a predetermined number of logic elements, one or more control signals distributed among the predetermined number of logic elements in the LAB, and LAB lines spanning between logic elements in different LABs in the array. In various embodiments, the LAB lines are arranged in a staggered pattern with a predetermined pitch between the lines. In other embodiments, the control signals of adjacent LABs can overlap, allowing control signals to be routed to the logic elements of adjacent LABs.

摘要翻译： 具有LAB互连线的PLD，跨越阵列中的相邻LAB并具有互连不同LAB中的两个逻辑元件的能力。 PLD包括布置在阵列中的多个LAB和将阵列的LAB互连的多个LAB线。 每个LAB包括预定数量的逻辑元件，分布在LAB中的预定数量的逻辑元件中的一个或多个控制信号，以及跨越阵列中不同LAB中的逻辑元件之间的LAB线。 在各种实施例中，LAB线以两条线之间的预定间距以交错图案排列。 在其他实施例中，相邻LAB的控制信号可以重叠，允许控制信号被路由到相邻LAB的逻辑元件。

公开(公告)号：US08788550B1

公开(公告)日：2014-07-22

申请号：US12484010

申请日：2009-06-12

申请人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

发明人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

IPC分类号： G06F7/38

CPC分类号： G06F7/575 ,  H03K19/177 ,  H03K19/17728

摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

摘要翻译： 可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。 至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个 二进制输入信号的算术组合的多级。 输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。 输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。 所描述的LUT可以有效地执行算术，以及非算术函数。

公开(公告)号：US08581624B2

公开(公告)日：2013-11-12

申请号：US13434847

申请日：2012-03-29

申请人： David Cashman ,  David Lewis ,  Valavan Manohararajah

发明人： David Cashman ,  David Lewis ,  Valavan Manohararajah

IPC分类号： H03K19/173

CPC分类号： H03K19/17728

摘要： A programmable logic region on a programmable integrated circuit may include a first set of look-up tables that receive programmable logic region input signals and a second set of look-up tables that produce programmable logic region output signals. Multiplexer circuitry may be interposed between the first and second sets of look-up tables. The multiplexer circuitry may receive the programmable logic region input signals in parallel with the output signals from the first set of look-up tables and may provide corresponding selected signals to the second set of look-up tables. The programmable logic region input signals may be shared by the first and second sets of look-up tables. Logic circuitry may be coupled to outputs of the first and second sets of look-up tables. The logic circuitry may be configured to logically combine output signals from the first and second sets of look-up tables.

摘要翻译： 可编程集成电路上的可编程逻辑区域可以包括接收可编程逻辑区域输入信号的第一组查询表和产生可编程逻辑区域输出信号的第二组查找表。 多路复用器电路可以插入在第一组和第二组查找表之间。 多路复用器电路可以与来自第一组查找表的输出信号并行地接收可编程逻辑区域输入信号，并且可以向第二组查找表提供相应的所选择的信号。 可编程逻辑区域输入信号可以由第一组和第二组查找表共享。 逻辑电路可以耦合到第一组和第二组查找表的输出。 逻辑电路可以被配置为逻辑地组合来自第一组和第二组查找表的输出信号。

公开(公告)号：US08222921B2

公开(公告)日：2012-07-17

申请号：US12987977

申请日：2011-01-10

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/173 ,  H03K19/094 ,  H03B19/00 ,  H03L7/00

CPC分类号： H03K19/1733 ,  G06F17/5054 ,  G06F2217/84

摘要： Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

摘要翻译： 为诸如可编程逻辑器件的电路提供可配置的时间借用触发器。 触发器可以基于可配置的延迟电路和两个锁存器，或者可以基于可配置的脉冲发生电路和单个锁存器。 在基于两个锁存器的设计中，串联布置第一和第二闩锁。 使用可配置的延迟电路延迟时钟信号。 已经加载了配置数据的可编程存储器元件可以用于调整可配置延迟电路产生多少延迟。 时钟信号的延迟版本被提供给与第一锁存器相关联的时钟输入。 第二个锁存器具有时钟输入端，无延迟地接收时钟信号。 在基于单个锁存器的设计中，可配置脉冲发生电路接收触发器的时钟信号，并为锁存器产生相应的时钟脉冲。

公开(公告)号：US20110102017A1

公开(公告)日：2011-05-05

申请号：US12987977

申请日：2011-01-10

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/173

CPC分类号： H03K19/1733 ,  G06F17/5054 ,  G06F2217/84

摘要： Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

摘要翻译： 为诸如可编程逻辑器件的电路提供可配置的时间借用触发器。 触发器可以基于可配置的延迟电路和两个锁存器，或者可以基于可配置的脉冲发生电路和单个锁存器。 在基于两个锁存器的设计中，串联布置第一和第二闩锁。 使用可配置的延迟电路延迟时钟信号。 已经加载了配置数据的可编程存储器元件可以用于调整可配置延迟电路产生多少延迟。 时钟信号的延迟版本被提供给与第一锁存器相关联的时钟输入。 第二个锁存器具有时钟输入端，无延迟地接收时钟信号。 在基于单个锁存器的设计中，可配置脉冲发生电路接收触发器的时钟信号，并为锁存器产生相应的时钟脉冲。

公开(公告)号：US20090278566A1

公开(公告)日：2009-11-12

申请号：US12505451

申请日：2009-07-17

申请人： David Lewis ,  David Cashman

发明人： David Lewis ,  David Cashman

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/1733 ,  G06F17/5054 ,  G06F2217/84

摘要： Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second latch are arranged in series. A clock signal is delayed using a configurable delay circuit. Programmable memory elements that have been loaded with configuration data may be used to adjust how much delay is produced by the configurable delay circuit. The delayed version of the clock signal is provided to a clock input associated with the first latch. The second latch has a clock input that receives the clock signal without delay. In designs based on a single latch, a configurable pulse generation circuit receives a clock signal for the flip-flop and generates a corresponding clock pulse for the latch.

摘要翻译： 为诸如可编程逻辑器件的电路提供可配置的时间借用触发器。 触发器可以基于可配置的延迟电路和两个锁存器，或者可以基于可配置的脉冲发生电路和单个锁存器。 在基于两个锁存器的设计中，串联布置第一和第二闩锁。 使用可配置的延迟电路延迟时钟信号。 已经加载了配置数据的可编程存储器元件可以用于调整可配置延迟电路产生多少延迟。 时钟信号的延迟版本被提供给与第一锁存器相关联的时钟输入。 第二个锁存器具有时钟输入端，无延迟地接收时钟信号。 在基于单个锁存器的设计中，可配置脉冲发生电路接收触发器的时钟信号，并为锁存器产生相应的时钟脉冲。

公开(公告)号：US08115530B2

公开(公告)日：2012-02-14

申请号：US12976752

申请日：2010-12-22

申请人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

发明人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

IPC分类号： H03K3/00

CPC分类号： H03K3/0375

摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器显示出通过条件降低的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。