-
公开(公告)号：US07732287B2
公开(公告)日：2010-06-08
申请号：US11415703
申请日：2006-05-02
申请人： Paul S. Fechner , Gordon A. Shaw , Eric E. Vogt
发明人： Paul S. Fechner , Gordon A. Shaw , Eric E. Vogt
IPC分类号： H01L21/336
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie that is shared between at least two FETs. A second trench may also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.
摘要翻译： 一种形成身体的方法。 该方法包括在SOI工艺的STI方案期间形成体系。 在STI方案中，形成第一沟槽。 第一沟槽在SOI衬底的掩埋氧化物层之前停止。 第一沟槽可以确定在至少两个FET之间共享的身体连接的高度。 也可以在第一沟槽内形成第二沟槽。 第二沟槽在SOI衬底中停止。 第二个沟槽定义了一个领带的位置和形状。 一旦定义了身体领带的位置和形状，就会在身体绑带上方沉积氧化物。 沉积的氧化物防止某些植入物进入身体束带。 通过防止这些植入物，源极和漏极注入可以与源极和漏极区域自对准，而不需要使用光致抗蚀剂掩模来屏蔽源极和漏极植入物的主体连接区域。
-
2.发明申请Fabrication process for silicon-on-insulator field effect transistors using high temperature nitrogen annealing 审中-公开使用高温氮退火的绝缘体上硅场效应晶体管的制造工艺公开(公告)号：US20080254590A1
公开(公告)日：2008-10-16
申请号：US11783598
申请日：2007-04-10
申请人： Eric E. Vogt , Paul S. Fechner
发明人： Eric E. Vogt , Paul S. Fechner
IPC分类号： H01L21/76
CPC分类号： H01L21/76283 , H01L21/84 , H01L27/1203
摘要： Disclosed is a method of fabricating a silicon-on-insulator (SOI) device that enables high device densities and mitigates variances in carrier mobility and saturation drain current (Idsat). The fabrication method incorporates one or more high temperature nitrogen anneal processes. The high temperature nitrogen anneal nitridizes the interfaces between the n-well and p-well silicon islands and the buried oxide layer. The high temperature nitrogen anneal also nitridizes the interfaces between the n-well and p-well silicon islands and the shallow trench isolation structure. The presence of diffused nitrogen at these interfaces substantially prevents compressive stresses on the n-well and p-well silicon islands, and substantially prevents upward bending of the n-well and p-well silicon islands, which cause variances in carrier mobility and Idsat.
摘要翻译： 公开了一种制造绝缘体上硅（SOI）器件的方法，其能够实现高器件密度并减轻载流子迁移率和饱和漏极电流的变化（Id）。 该制造方法包括一个或多个高温氮退火工艺。 高温氮退火使n阱和p阱硅岛和掩埋氧化物层之间的界面氮化。 高温氮退火还使n阱和p阱硅岛与浅沟槽隔离结构之间的界面氮化。 在这些界面处扩散氮的存在基本上防止了n阱和p阱硅岛上的压缩应力，并且基本上防止了n阱和p阱硅岛的向上弯曲，这导致载流子迁移率的变化， SUB> sat 。
-
公开(公告)号：US07183042B2
公开(公告)日：2007-02-27
申请号：US10706067
申请日：2003-11-12
IPC分类号： G03F7/20
CPC分类号： G11C11/16
摘要： In a process of making a magnetoresistive memory device, a mask layout is produced by use of any suitable design tool. The mask layout is laid out in grids having a central grid forming a central section and grids forming bit end sections, and the grids of the bit end sections are rectangles. A mask is made by use of the mask layout, and the mask has stepped bit ends. The mask is used to make a magnetic storage layer having tapered bit ends, to make a magnetic sense layer having tapered bit ends, and to make a non-magnetic layer having tapered bit ends. The non-magnetic layer is between the magnetic sense layer and the magnetic storage layer.
摘要翻译： 在制造磁阻存储器件的过程中，通过使用任何合适的设计工具来生产掩模布局。 掩模布局布置在具有形成中心部分的中心格栅和形成钻头末端部分的格栅的格栅中，钻头端部的格栅为矩形。 使用掩模布局制作掩模，并且掩模具有阶梯位。 该掩模用于制造具有锥形位端的磁存储层，以形成具有锥形位端的磁感应层，并制成具有锥形位端的非磁性层。 非磁性层位于磁感应层和磁性存储层之间。
-
公开(公告)号：US20080233704A1
公开(公告)日：2008-09-25
申请号：US11690379
申请日：2007-03-23
申请人： Paul S. Fechner , Gordon A. Shaw
发明人： Paul S. Fechner , Gordon A. Shaw
IPC分类号： H01L21/20
CPC分类号： H01L23/5228 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the circuit. The resistor capacitor structure may be formed on top or within interlevel dielectric layers. The resistance layer, alternatively, may be used to fill a cavity located between interlevel dielectric layers and accordingly provide a resistance path between the interlevel dielectric layers.
摘要翻译： 一种电阻电容器结构及其制造方法。 电阻电容器结构在微电子电路内的至少两个节点之间提供电容。 电阻电容器结构的底板包括电阻层，其又在电路内的附加节点之间提供电阻路径。 电阻器电容器结构可以形成在层间电介质层的顶部或内部。 可选地，电阻层可以用于填充位于层间电介质层之间的空腔，并因此在层间电介质层之间提供电阻路径。
-
公开(公告)号：US20120228513A1
公开(公告)日：2012-09-13
申请号：US13424269
申请日：2012-03-19
IPC分类号： G01T1/24
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
-
6.发明申请Non-Planar Silicon-On-Insulator Device that Includes an "Area-Efficient" Body Tie 有权包含“区域高效”身体领带的非平面矽绝缘体设备公开(公告)号：US20090065866A1
公开(公告)日：2009-03-12
申请号：US11853611
申请日：2007-09-11
IPC分类号： H01L29/786
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/78615
摘要： Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.
摘要翻译： 公开了包括“面积效率”的身体搭接的非平面SOI器件。 该器件包括体基片，形成在本体基片的表面上的绝缘体层，以及形成在绝缘体层的表面上的硅体。 硅体优选地包括（i）连接源极区域和漏极区域的非平面沟道，以及（ii）与沟道相邻并且将沟道耦合到电压电位的主体连接。 该器件还包括形成在沟道上的栅极电介质和形成在栅极电介质上的栅极材料。
-
公开(公告)号：US06433983B1
公开(公告)日：2002-08-13
申请号：US09449312
申请日：1999-11-24
申请人： Paul S. Fechner
发明人： Paul S. Fechner
IPC分类号： H02G900
CPC分类号： H01L27/11898 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An output buffer with built-in ESD protection is disclosed. The built-in ESD protection is preferably formed using transistors from the sea-of-transistors or sea-of-gates region of the integrated circuit, which may eliminate the need for dedicated ESD devices, and in particular, dedicated ESD devices that are pre-fabricated into the under-layers in and around the perimeter of the integrated circuit.
摘要翻译： 公开了具有内置ESD保护的输出缓冲器。 内置的ESD保护优选使用来自集成电路的晶体管或晶体管的区域的晶体管形成，这可以消除对专用ESD器件的需要，特别是预先设置的专用ESD器件 - 集成到集成电路周边和周围的下层。
-
公开(公告)号：US08742831B2
公开(公告)日：2014-06-03
申请号：US12390792
申请日：2009-02-23
申请人： Paul S. Fechner
发明人： Paul S. Fechner
CPC分类号： G05F1/46 , H03F1/301 , H03F1/304 , H03F2200/366
摘要： A method for digital programmable optimization of a mixed-signal circuit is provided. The method comprises dividing up one or more transistor devices of the mixed-signal circuit into one or more transistor segments, with each transistor segment including a body tie bias terminal. Each body tie bias terminal is coupled to at least one voltage bias, either by placing each body tie bias terminal in signal communication with one or more bias nodes in the mixed-signal circuit, or by placing each body tie bias terminal in signal communication with a non-precision bias voltage source. Each body tie terminal is also arranged to be in signal communication with a separate one of one or more digital programmable storage elements.
摘要翻译： 提供了一种用于混合信号电路的数字可编程优化的方法。 该方法包括将混合信号电路的一个或多个晶体管器件分成一个或多个晶体管段，其中每个晶体管段包括主体偏置端子。 每个主体连接偏置端子通过将每个主体连接偏置端子与混合信号电路中的一个或多个偏置节点进行信号通信，或者通过将每个主体连接偏置端子与信号通信置于信号通信中来耦合至少一个电压偏置 非精密偏置电压源。 每个身体接合终端还被布置成与一个或多个数字可编程存储元件中的单独的一个信号通信。
-
公开(公告)号：US08399845B2
公开(公告)日：2013-03-19
申请号：US13424269
申请日：2012-03-19
IPC分类号： G01T3/00
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
-
10.发明授权MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates 失效MOS器件具有与用于绝缘体上硅衬底上的体注入电流限制特征的门到体连接的MOS器件
公开(公告)号：US5753955A
公开(公告)日：1998-05-19
申请号：US770616
申请日：1996-12-19
申请人： Paul S. Fechner
发明人： Paul S. Fechner
IPC分类号： H01L29/786 , H01L27/01 , H01L27/095 , H01L27/12 , H01L29/861
CPC分类号： H01L29/78696
摘要： A MOS transistor formed in a silicon on insulator structure includes a rectifying connection between a body portion and the gate. The connection decreases the threshold voltage of the transistor in the reverse bias state and limits a difference in voltage between the body and gate in the forward bias state of the rectifying contact.
摘要翻译： 形成在绝缘体上的结构的MOS晶体管包括主体部分和栅极之间的整流连接。 该连接降低了反向偏置状态下晶体管的阈值电压，并限制了整流触点正向偏置状态下的主体与栅极之间的电压差。
-
-
-
-
-
-
-
-
-
搜索结果
30 条记录 (耗时 0.019 秒)