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1.发明授权Test structure for locating electromigration voids in dual damascene interconnects 失效用于定位双镶嵌互连中电迁移空隙的测试结构公开(公告)号：US06995392B2
公开(公告)日：2006-02-07
申请号：US10214546
申请日：2002-08-07
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure is disclosed for locating electromigration voids in a semiconductor interconnect structure having an interconnect via interconnecting a lower metallization line with an upper metallization line. In an exemplary embodiment, the test structure includes a via portion the top of the interconnect via at the upper metallization line. In addition, a line portion extends from the via portion, wherein the line portion connects to an external probing surface, in addition to a probing surface on the lower metallization line, thereby allowing the identification of any electromigration voids present in the interconnect via.
摘要翻译： 公开了一种测试结构，用于通过将下部金属化线与上部金属化线相互连接来定位具有互连的半导体互连结构中的电迁移空穴。 在示例性实施例中，测试结构包括在上金属化线处的互连通孔的顶部的通孔部分。 此外，线路部分从通孔部分延伸，其中线部分连接到外部探测表面，以及下部金属化线上的探测表面，从而允许识别互连通孔中存在的任何电迁移空隙。
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公开(公告)号：US08922022B2
公开(公告)日：2014-12-30
申请号：US13356013
申请日：2012-01-23
IPC分类号： H01L23/48 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译： 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。
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3.发明授权Structure and method for monitoring stress-induced degradation of conductive interconnects 有权用于监测导电互连的应力诱导退化的结构和方法公开(公告)号：US07397260B2
公开(公告)日：2008-07-08
申请号：US11163948
申请日：2005-11-04
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。
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4.发明授权公开(公告)号：US07692439B2
公开(公告)日：2010-04-06
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译： 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。
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公开(公告)号：US20120119366A1
公开(公告)日：2012-05-17
申请号：US13356013
申请日：2012-01-23
IPC分类号： H01L23/532
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译： 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。
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公开(公告)号：US08114768B2
公开(公告)日：2012-02-14
申请号：US12344838
申请日：2008-12-29
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译： 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。
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公开(公告)号：US20100164116A1
公开(公告)日：2010-07-01
申请号：US12344838
申请日：2008-12-29
IPC分类号： H01L23/52 , H01L21/4763 , H01L23/48 , H01L21/768
CPC分类号： H01L21/76816 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A liner-to-liner direct contact is formed between an upper metallic liner of a conductive via and a lower metallic liner of a metal line below. The liner-to-liner contact impedes abrupt electromigration failures and enhances electromigration resistance of the metal interconnect structure. The at least one dielectric material portion may include a plurality of dielectric material portions arranged to insure direct contact of between the upper metallic liner and the lower metallic liner. Alternatively, the at least one dielectric material portion may comprise a single dielectric portion of which the area has a sufficient lateral overlap with the area of the conductive via to insure that a liner-to-liner direct contact is formed within the range of allowed lithographic overlay variations.
摘要翻译： 在导电通孔的上金属衬套和下面的金属线的下金属衬垫之间形成衬管到衬垫直接接触。 衬套到衬垫接触件阻止突然的电迁移故障并增强金属互连结构的电迁移阻力。 所述至少一个电介质材料部分可以包括多个电介质材料部分，其布置成确保上金属衬垫和下金属衬垫之间的直接接触。 或者，所述至少一个介电材料部分可以包括单个电介质部分，其中该区域具有与导电通孔的面积的足够的横向重叠，以确保在允许的光刻的范围内形成衬管到衬垫的直接接触 重叠变化。
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8.发明申请公开(公告)号：US20080231312A1
公开(公告)日：2008-09-25
申请号：US12154304
申请日：2008-05-22
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.
摘要翻译： 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。
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9.发明授权Structure for monitoring stress-induced degradation of conductive interconnects 失效用于监测导电互连的应力导致退化的结构公开(公告)号：US07639032B2
公开(公告)日：2009-12-29
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。
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10.发明授权公开(公告)号：US08726201B2
公开(公告)日：2014-05-13
申请号：US12780138
申请日：2010-05-14
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/10
摘要： A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.
摘要翻译： 一种用于预测半导体产品中多个电迁移关键元件的方法和系统。 该方法包括使用运行在计算机设备上的设计工具并且基于增加的可靠性温度和增加的预期电流中的至少一个来确定电路设计库中的多个库元件的关键要素因子。 该方法还包括：（i）产品中包含的多个库元素中的相应数量的数量，以及（ii）关键要素因素来确定产品中的关键元素的数量。
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